dds_sin.tan.qmsg

用vhdl编写的程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "bb register register ddsc:i_dds\|bbcnt1\[2\] ddsc:i_dds\|bbcnt1\[3\] 275.03 MHz Internal " "Info: Clock \"bb\" Internal fmax is restricted to 275.03 MHz between source register \"ddsc:i_dds\|bbcnt1\[2\]\" and destination register \"ddsc:i_dds\|bbcnt1\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.290 ns + Longest register register " "Info: + Longest register to register delay is 1.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddsc:i_dds\|bbcnt1\[2\] 1 REG LC_X17_Y13_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y13_N2; Fanout = 4; REG Node = 'ddsc:i_dds\|bbcnt1\[2\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { ddsc:i_dds|bbcnt1[2] } "NODE_NAME" } "" } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.738 ns) 1.290 ns ddsc:i_dds\|bbcnt1\[3\] 2 REG LC_X17_Y13_N5 3 " "Info: 2: + IC(0.552 ns) + CELL(0.738 ns) = 1.290 ns; Loc. = LC_X17_Y13_N5; Fanout = 3; REG Node = 'ddsc:i_dds\|bbcnt1\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.290 ns" { ddsc:i_dds|bbcnt1[2] ddsc:i_dds|bbcnt1[3] } "NODE_NAME" } "" } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 57.21 % ) " "Info: Total cell delay = 0.738 ns ( 57.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.552 ns ( 42.79 % ) " "Info: Total interconnect delay = 0.552 ns ( 42.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.290 ns" { ddsc:i_dds|bbcnt1[2] ddsc:i_dds|bbcnt1[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "1.290 ns" { ddsc:i_dds|bbcnt1[2] ddsc:i_dds|bbcnt1[3] } { 0.000ns 0.552ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bb destination 7.324 ns + Shortest register " "Info: + Shortest clock path from clock \"bb\" to destination register is 7.324 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns bb 1 CLK PIN_35 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_35; Fanout = 4; CLK Node = 'bb'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { bb } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.144 ns) + CELL(0.711 ns) 7.324 ns ddsc:i_dds\|bbcnt1\[3\] 2 REG LC_X17_Y13_N5 3 " "Info: 2: + IC(5.144 ns) + CELL(0.711 ns) = 7.324 ns; Loc. = LC_X17_Y13_N5; Fanout = 3; REG Node = 'ddsc:i_dds\|bbcnt1\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "5.855 ns" { bb ddsc:i_dds|bbcnt1[3] } "NODE_NAME" } "" } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_s