📄 dds_sin.tan.qmsg

📁 用vhdl编写的程序
💻 QMSG
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{ "Info" "ITDB_FULL_SLACK_RESULT" "sysclk memory ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|ram_block1a1~porta_address_reg9 register ddsout_rom\[8\] -9.605 ns " "Info: Slack time is -9.605 ns for clock \"sysclk\" between source memory \"ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|ram_block1a1~porta_address_reg9\" and destination register \"ddsout_rom\[8\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.548 ns + Largest memory register " "Info: + Largest memory to register requirement is 0.548 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.833 ns + " "Info: + Setup relationship between source and destination is 0.833 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 1.000 ns " "Info: + Latch edge is 1.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination sysclk 10.000 ns 5.000 ns inverted 50 " "Info: Clock period of Destination clock \"sysclk\" is 10.000 ns with inverted offset of 5.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.167 ns " "Info: - Launch edge is 0.167 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ppl2_5:ppl\|altpll:altpll_component\|_clk0 4.000 ns -1.833 ns  50 " "Info: Clock period of Source clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" is 4.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.402 ns + Largest " "Info: + Largest clock skew is 0.402 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sysclk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"sysclk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sysclk 1 CLK PIN_17 198 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 198; CLK Node = 'sysclk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { sysclk } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns ddsout_rom\[8\] 2 REG LC_X11_Y3_N7 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X11_Y3_N7; Fanout = 2; REG Node = 'ddsout_rom\[8\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.261 ns" { sysclk ddsout_rom[8] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.730 ns" { sysclk ddsout_rom[8] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.730 ns" { sysclk sysclk~out0 ddsout_rom[8] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ppl2_5:ppl\|altpll:altpll_component\|_clk0 source 2.328 ns - Longest memory " "Info: - Longest clock path from clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" to source memory is 2.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ppl2_5:ppl\|altpll:altpll_component\|_clk0 1 CLK PLL_1 268 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 268; CLK Node = 'ppl2_5:ppl\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { ppl2_5:ppl|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.606 ns) + CELL(0.722 ns) 2.328 ns ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|ram_block1a1~porta_address_reg9 2 MEM M4K_X13_Y10 4 " "Info: 2: + IC(1.606 ns) + CELL(0.722 ns) = 2.328 ns; Loc. = M4K_X13_Y10; Fanout = 4; MEM Node = 'ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } "" } } { "db/altsyncram_jqo.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_jqo.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 31.01 % ) " "Info: Total cell delay = 0.722 ns ( 31.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.606 ns ( 68.99 % ) " "Info: Total interconnect delay = 1.606 ns ( 68.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.606ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.730 ns" { sysclk ddsout_rom[8] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.730 ns" { sysclk sysclk~out0 ddsout_rom[8] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.606ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_jqo.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_jqo.tdf" 62 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 199 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.730 ns" { sysclk ddsout_rom[8] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.730 ns" { sysclk sysclk~out0 ddsout_rom[8] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.606ns } { 0.000ns 0.722ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.153 ns - Longest memory register " "Info: - Longest memory to register delay is 10.153 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|ram_block1a1~porta_address_reg9 1 MEM M4K_X13_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y10; Fanout = 4; MEM Node = 'ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } "" } } { "db/altsyncram_jqo.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_jqo.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|q_a\[1\] 2 MEM M4K_X13_Y10 5 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y10; Fanout = 5; MEM Node = 'ddsc:i_dds\|lpm_rom:i_rom1\|altrom:srom\|altsyncram:rom_block\|altsyncram_jqo:auto_generated\|q_a\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "4.308 ns" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_jqo.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_jqo.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.575 ns) 6.469 ns ddsc:i_dds\|add~1283COUT1_1348 3 COMB LC_X15_Y6_N6 2 " "Info: 3: + IC(1.586 ns) + CELL(0.575 ns) = 6.469 ns; Loc. = LC_X15_Y6_N6; Fanout = 2; COMB Node = 'ddsc:i_dds\|add~1283COUT1_1348'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.161 ns" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] ddsc:i_dds|add~1283COUT1_1348 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.549 ns ddsc:i_dds\|add~1288COUT1_1350 4 COMB LC_X15_Y6_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 6.549 ns; Loc. = LC_X15_Y6_N7; Fanout = 2; COMB Node = 'ddsc:i_dds\|add~1288COUT1_1350'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.080 ns" { ddsc:i_dds|add~1283COUT1_1348 ddsc:i_dds|add~1288COUT1_1350 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 6.629 ns ddsc:i_dds\|add~1293COUT1_1352 5 COMB LC_X15_Y6_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 6.629 ns; Loc. = LC_X15_Y6_N8; Fanout = 2; COMB Node = 'ddsc:i_dds\|add~1293COUT1_1352'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.080 ns" { ddsc:i_dds|add~1288COUT1_1350 ddsc:i_dds|add~1293COUT1_1352 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 6.887 ns ddsc:i_dds\|add~1298 6 COMB LC_X15_Y6_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 6.887 ns; Loc. = LC_X15_Y6_N9; Fanout = 6; COMB Node = 'ddsc:i_dds\|add~1298'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.258 ns" { ddsc:i_dds|add~1293COUT1_1352 ddsc:i_dds|add~1298 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 7.566 ns ddsc:i_dds\|add~1321 7 COMB LC_X15_Y5_N4 1 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 7.566 ns; Loc. = LC_X15_Y5_N4; Fanout = 1; COMB Node = 'ddsc:i_dds\|add~1321'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.679 ns" { ddsc:i_dds|add~1298 ddsc:i_dds|add~1321 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.114 ns) 9.366 ns ddsout_rom~793 8 COMB LC_X11_Y3_N5 1 " "Info: 8: + IC(1.686 ns) + CELL(0.114 ns) = 9.366 ns; Loc. = LC_X11_Y3_N5; Fanout = 1; COMB Node = 'ddsout_rom~793'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.800 ns" { ddsc:i_dds|add~1321 ddsout_rom~793 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.662 ns ddsout_rom~794 9 COMB LC_X11_Y3_N6 1 " "Info: 9: + IC(0.182 ns) + CELL(0.114 ns) = 9.662 ns; Loc. = LC_X11_Y3_N6; Fanout = 1; COMB Node = 'ddsout_rom~794'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.296 ns" { ddsout_rom~793 ddsout_rom~794 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 10.153 ns ddsout_rom\[8\] 10 REG LC_X11_Y3_N7 2 " "Info: 10: + IC(0.182 ns) + CELL(0.309 ns) = 10.153 ns; Loc. = LC_X11_Y3_N7; Fanout = 2; REG Node = 'ddsout_rom\[8\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.491 ns" { ddsout_rom~794 ddsout_rom[8] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.517 ns ( 64.19 % ) " "Info: Total cell delay = 6.517 ns ( 64.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.636 ns ( 35.81 % ) " "Info: Total interconnect delay = 3.636 ns ( 35.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "10.153 ns" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] ddsc:i_dds|add~1283COUT1_1348 ddsc:i_dds|add~1288COUT1_1350 ddsc:i_dds|add~1293COUT1_1352 ddsc:i_dds|add~1298 ddsc:i_dds|add~1321 ddsout_rom~793 ddsout_rom~794 ddsout_rom[8] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "10.153 ns" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] ddsc:i_dds|add~1283COUT1_1348 ddsc:i_dds|add~1288COUT1_1350 ddsc:i_dds|add~1293COUT1_1352 ddsc:i_dds|add~1298 ddsc:i_dds|add~1321 ddsout_rom~793 ddsout_rom~794 ddsout_rom[8] } { 0.000ns 0.000ns 1.586ns 0.000ns 0.000ns 0.000ns 0.000ns 1.686ns 0.182ns 0.182ns } { 0.000ns 4.308ns 0.575ns 0.080ns 0.080ns 0.258ns 0.679ns 0.114ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.730 ns" { sysclk ddsout_rom[8] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.730 ns" { sysclk sysclk~out0 ddsout_rom[8] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.328 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.606ns } { 0.000ns 0.722ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "10.153 ns" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] ddsc:i_dds|add~1283COUT1_1348 ddsc:i_dds|add~1288COUT1_1350 ddsc:i_dds|add~1293COUT1_1352 ddsc:i_dds|add~1298 ddsc:i_dds|add~1321 ddsout_rom~793 ddsout_rom~794 ddsout_rom[8] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "10.153 ns" { ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9 ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] ddsc:i_dds|add~1283COUT1_1348 ddsc:i_dds|add~1288COUT1_1350 ddsc:i_dds|add~1293COUT1_1352 ddsc:i_dds|add~1298 ddsc:i_dds|add~1321 ddsout_rom~793 ddsout_rom~794 ddsout_rom[8] } { 0.000ns 0.000ns 1.586ns 0.000ns 0.000ns 0.000ns 0.000ns 1.686ns 0.182ns 0.182ns } { 0.000ns 4.308ns 0.575ns 0.080ns 0.080ns 0.258ns 0.679ns 0.114ns 0.114ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'sysclk' 1134 " "Warning: Can't achieve timing requirement Clock Setup: 'sysclk' along 1134 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "amp register register count\[1\] count\[7\] 275.03 MHz Internal " "Info: Clock \"amp\" Internal fmax is restricted to 275.03 MHz between source register \"count\[1\]\" and destination register \"count\[7\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.266 ns + Longest register register " "Info: + Longest register to register delay is 2.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X25_Y13_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y13_N1; Fanout = 4; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { count[1] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns count\[1\]~61 2 COMB LC_X25_Y13_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X25_Y13_N1; Fanout = 2; COMB Node = 'count\[1\]~61'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.093 ns" { count[1] count[1]~61 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns count\[2\]~65 3 COMB LC_X25_Y13_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X25_Y13_N2; Fanout = 2; COMB Node = 'count\[2\]~65'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.078 ns" { count[1]~61 count[2]~65 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns count\[3\]~69 4 COMB LC_X25_Y13_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X25_Y13_N3; Fanout = 2; COMB Node = 'count\[3\]~69'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.078 ns" { count[2]~65 count[3]~69 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns count\[4\]~73 5 COMB LC_X25_Y13_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X25_Y13_N4; Fanout = 3; COMB Node = 'count\[4\]~73'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.178 ns" { count[3]~69 count[4]~73 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.266 ns count\[7\] 6 REG LC_X25_Y13_N7 2 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X25_Y13_N7; Fanout = 2; REG Node = 'count\[7\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.839 ns" { count[4]~73 count[7] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns ( 76.65 % ) " "Info: Total cell delay = 1.737 ns ( 76.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 23.35 % ) " "Info: Total interconnect delay = 0.529 ns ( 23.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.266 ns" { count[1] count[1]~61 count[2]~65 count[3]~69 count[4]~73 count[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.266 ns" { count[1] count[1]~61 count[2]~65 count[3]~69 count[4]~73 count[7] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "amp destination 9.132 ns + Shortest register " "Info: + Shortest clock path from clock \"amp\" to destination register is 9.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns amp 1 CLK PIN_143 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 8; CLK Node = 'amp'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { amp } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.946 ns) + CELL(0.711 ns) 9.132 ns count\[7\] 2 REG LC_X25_Y13_N7 2 " "Info: 2: + IC(6.946 ns) + CELL(0.711 ns) = 9.132 ns; Loc. = LC_X25_Y13_N7; Fanout = 2; REG Node = 'count\[7\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.657 ns" { amp count[7] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 23.94 % ) " "Info: Total cell delay = 2.186 ns ( 23.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.946 ns ( 76.06 % ) " "Info: Total interconnect delay = 6.946 ns ( 76.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "9.132 ns" { amp count[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.132 ns" { amp amp~out0 count[7] } { 0.000ns 0.000ns 6.946ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "amp source 9.132 ns - Longest register " "Info: - Longest clock path from clock \"amp\" to source register is 9.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns amp 1 CLK PIN_143 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_143; Fanout = 8; CLK Node = 'amp'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { amp } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.946 ns) + CELL(0.711 ns) 9.132 ns count\[1\] 2 REG LC_X25_Y13_N1 4 " "Info: 2: + IC(6.946 ns) + CELL(0.711 ns) = 9.132 ns; Loc. = LC_X25_Y13_N1; Fanout = 4; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.657 ns" { amp count[1] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 23.94 % ) " "Info: Total cell delay = 2.186 ns ( 23.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.946 ns ( 76.06 % ) " "Info: Total interconnect delay = 6.946 ns ( 76.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "9.132 ns" { amp count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.132 ns" { amp amp~out0 count[1] } { 0.000ns 0.000ns 6.946ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "9.132 ns" { amp count[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.132 ns" { amp amp~out0 count[7] } { 0.000ns 0.000ns 6.946ns } { 0.000ns 1.475ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "9.132 ns" { amp count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.132 ns" { amp amp~out0 count[1] } { 0.000ns 0.000ns 6.946ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.266 ns" { count[1] count[1]~61 count[2]~65 count[3]~69 count[4]~73 count[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.266 ns" { count[1] count[1]~61 count[2]~65 count[3]~69 count[4]~73 count[7] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "9.132 ns" { amp count[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.132 ns" { amp amp~out0 count[7] } { 0.000ns 0.000ns 6.946ns } { 0.000ns 1.475ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "9.132 ns" { amp count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "9.132 ns" { amp amp~out0 count[1] } { 0.000ns 0.000ns 6.946ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { count[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { count[7] } {  } {  } } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 210 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
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