dds_sin.tan.qmsg

用vhdl编写的程序

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "ppl2_5:ppl\|altpll:altpll_component\|_clk0 register QRD\[3\] register QRD\[0\] -244 ps " "Info: Slack time is -244 ps for clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" between source register \"QRD\[3\]\" and destination register \"QRD\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "235.63 MHz 4.244 ns " "Info: Fmax is 235.63 MHz (period= 4.244 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.739 ns + Largest register register " "Info: + Largest register to register requirement is 3.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "4.000 ns + " "Info: + Setup relationship between source and destination is 4.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 2.167 ns " "Info: + Latch edge is 2.167 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination ppl2_5:ppl\|altpll:altpll_component\|_clk0 4.000 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" is 4.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source ppl2_5:ppl\|altpll:altpll_component\|_clk0 4.000 ns -1.833 ns  50 " "Info: Clock period of Source clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" is 4.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ppl2_5:ppl\|altpll:altpll_component\|_clk0 destination 7.214 ns + Shortest register " "Info: + Shortest clock path from clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" to destination register is 7.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ppl2_5:ppl\|altpll:altpll_component\|_clk0 1 CLK PLL_1 268 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 268; CLK Node = 'ppl2_5:ppl\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { ppl2_5:ppl|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.592 ns) + CELL(0.935 ns) 2.527 ns ddsc:i_dds\|acc\[22\] 2 REG LC_X8_Y10_N6 41 " "Info: 2: + IC(1.592 ns) + CELL(0.935 ns) = 2.527 ns; Loc. = LC_X8_Y10_N6; Fanout = 41; REG Node = 'ddsc:i_dds\|acc\[22\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.527 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] } "NODE_NAME" } "" } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 7.214 ns QRD\[0\] 3 REG LC_X12_Y3_N0 7 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 7.214 ns; Loc. = LC_X12_Y3_N0; Fanout = 7; REG Node = 'QRD\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "4.687 ns" { ddsc:i_dds|acc[22] QRD[0] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 22.82 % ) " "Info: Total cell delay = 1.646 ns ( 22.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.568 ns ( 77.18 % ) " "Info: Total interconnect delay = 5.568 ns ( 77.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ppl2_5:ppl\|altpll:altpll_component\|_clk0 source 7.214 ns - Longest register " "Info: - Longest clock path from clock \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" to source register is 7.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ppl2_5:ppl\|altpll:altpll_component\|_clk0 1 CLK PLL_1 268 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 268; CLK Node = 'ppl2_5:ppl\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { ppl2_5:ppl|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.592 ns) + CELL(0.935 ns) 2.527 ns ddsc:i_dds\|acc\[22\] 2 REG LC_X8_Y10_N6 41 " "Info: 2: + IC(1.592 ns) + CELL(0.935 ns) = 2.527 ns; Loc. = LC_X8_Y10_N6; Fanout = 41; REG Node = 'ddsc:i_dds\|acc\[22\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "2.527 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] } "NODE_NAME" } "" } } { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 7.214 ns QRD\[3\] 3 REG LC_X12_Y3_N3 7 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 7.214 ns; Loc. = LC_X12_Y3_N3; Fanout = 7; REG Node = 'QRD\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "4.687 ns" { ddsc:i_dds|acc[22] QRD[3] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 22.82 % ) " "Info: Total cell delay = 1.646 ns ( 22.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.568 ns ( 77.18 % ) " "Info: Total interconnect delay = 5.568 ns ( 77.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.983 ns - Longest register register " "Info: - Longest register to register delay is 3.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns QRD\[3\] 1 REG LC_X12_Y3_N3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y3_N3; Fanout = 7; REG Node = 'QRD\[3\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { QRD[3] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.590 ns) 1.424 ns rtl~184 2 COMB LC_X11_Y3_N9 1 " "Info: 2: + IC(0.834 ns) + CELL(0.590 ns) = 1.424 ns; Loc. = LC_X11_Y3_N9; Fanout = 1; COMB Node = 'rtl~184'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.424 ns" { QRD[3] rtl~184 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.292 ns) 2.152 ns QRD\[0\]~174 3 COMB LC_X11_Y3_N4 10 " "Info: 3: + IC(0.436 ns) + CELL(0.292 ns) = 2.152 ns; Loc. = LC_X11_Y3_N4; Fanout = 10; COMB Node = 'QRD\[0\]~174'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.728 ns" { rtl~184 QRD[0]~174 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(1.112 ns) 3.983 ns QRD\[0\] 4 REG LC_X12_Y3_N0 7 " "Info: 4: + IC(0.719 ns) + CELL(1.112 ns) = 3.983 ns; Loc. = LC_X12_Y3_N0; Fanout = 7; REG Node = 'QRD\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.831 ns" { QRD[0]~174 QRD[0] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 161 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.994 ns ( 50.06 % ) " "Info: Total cell delay = 1.994 ns ( 50.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.989 ns ( 49.94 % ) " "Info: Total interconnect delay = 1.989 ns ( 49.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "3.983 ns" { QRD[3] rtl~184 QRD[0]~174 QRD[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.983 ns" { QRD[3] rtl~184 QRD[0]~174 QRD[0] } { 0.000ns 0.834ns 0.436ns 0.719ns } { 0.000ns 0.590ns 0.292ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[0] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.214 ns" { ppl2_5:ppl|altpll:altpll_component|_clk0 ddsc:i_dds|acc[22] QRD[3] } { 0.000ns 1.592ns 3.976ns } { 0.000ns 0.935ns 0.711ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "3.983 ns" { QRD[3] rtl~184 QRD[0]~174 QRD[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.983 ns" { QRD[3] rtl~184 QRD[0]~174 QRD[0] } { 0.000ns 0.834ns 0.436ns 0.719ns } { 0.000ns 0.590ns 0.292ns 1.112ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'ppl2_5:ppl\|altpll:altpll_component\|_clk0' 30 " "Warning: Can't achieve timing requirement Clock Setup: 'ppl2_5:ppl\|altpll:altpll_component\|_clk0' along 30 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}