dds_sin.fit.qmsg

用vhdl编写的程序

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "cmp_select " "Warning: Node \"cmp_select\" is assigned to location or region, but does not exist in design" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "cmp_select" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:06 " "Info: Fitter placement operations ending: elapsed time is 00:00:06" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "15.859 ns register register " "Info: Estimated most critical path is register to register delay of 15.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|dataout_n\[14\] 1 REG LAB_X19_Y3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y3; Fanout = 4; REG Node = 'mul_6:mul\|kk:u1\|altmult_add:ALTMULT_ADD_component\|mult_add_rh23:auto_generated\|alt_mac_out:mac_out4\|dataout_n\[14\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14] } "NODE_NAME" } "" } } { "alt_mac_out.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/alt_mac_out.tdf" 402 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.471 ns) + CELL(0.575 ns) 1.046 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_pe8:add_sub_5\|add_sub_cella\[4\]~COUTCOUT1_79 2 COMB LAB_X19_Y3 1 " "Info: 2: + IC(0.471 ns) + CELL(0.575 ns) = 1.046 ns; Loc. = LAB_X19_Y3; Fanout = 1; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_pe8:add_sub_5\|add_sub_cella\[4\]~COUTCOUT1_79'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.046 ns" { mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14] mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~COUTCOUT1_79 } "NODE_NAME" } "" } } { "db/add_sub_pe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_pe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.654 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_pe8:add_sub_5\|add_sub_cella\[4\]~75 3 COMB LAB_X19_Y3 3 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.654 ns; Loc. = LAB_X19_Y3; Fanout = 3; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_pe8:add_sub_5\|add_sub_cella\[4\]~75'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.608 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~COUTCOUT1_79 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~75 } "NODE_NAME" } "" } } { "db/add_sub_pe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_pe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.442 ns) 2.545 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[39\]~1021 4 COMB LAB_X20_Y3 2 " "Info: 4: + IC(0.449 ns) + CELL(0.442 ns) = 2.545 ns; Loc. = LAB_X20_Y3; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[39\]~1021'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.891 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~75 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[39]~1021 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 3.210 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[46\]~1022 5 COMB LAB_X20_Y3 2 " "Info: 5: + IC(0.223 ns) + CELL(0.442 ns) = 3.210 ns; Loc. = LAB_X20_Y3; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[46\]~1022'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[39]~1021 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1022 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.292 ns) 3.875 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[46\]~1023 6 COMB LAB_X20_Y3 2 " "Info: 6: + IC(0.373 ns) + CELL(0.292 ns) = 3.875 ns; Loc. = LAB_X20_Y3; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[46\]~1023'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1022 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1023 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 4.540 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_7\|add_sub_cella\[5\]~142 7 COMB LAB_X20_Y3 2 " "Info: 7: + IC(0.223 ns) + CELL(0.442 ns) = 4.540 ns; Loc. = LAB_X20_Y3; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_7\|add_sub_cella\[5\]~142'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1023 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~142 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(0.292 ns) 5.949 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[53\]~1024 8 COMB LAB_X20_Y6 2 " "Info: 8: + IC(1.117 ns) + CELL(0.292 ns) = 5.949 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[53\]~1024'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "1.409 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~142 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[53]~1024 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 6.614 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_8\|add_sub_cella\[5\]~186 9 COMB LAB_X20_Y6 3 " "Info: 9: + IC(0.223 ns) + CELL(0.442 ns) = 6.614 ns; Loc. = LAB_X20_Y6; Fanout = 3; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_8\|add_sub_cella\[5\]~186'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[53]~1024 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~186 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 7.279 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_10\|add_sub_cella\[5\]~86 10 COMB LAB_X20_Y6 2 " "Info: 10: + IC(0.223 ns) + CELL(0.442 ns) = 7.279 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_10\|add_sub_cella\[5\]~86'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~186 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~86 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 7.944 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[67\]~1025 11 COMB LAB_X20_Y6 2 " "Info: 11: + IC(0.223 ns) + CELL(0.442 ns) = 7.944 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[67\]~1025'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~86 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[67]~1025 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 8.609 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_10\|add_sub_cella\[5\]~88 12 COMB LAB_X20_Y6 2 " "Info: 12: + IC(0.223 ns) + CELL(0.442 ns) = 8.609 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_10\|add_sub_cella\[5\]~88'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[67]~1025 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~88 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.292 ns) 9.274 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[74\]~1027 13 COMB LAB_X20_Y6 2 " "Info: 13: + IC(0.373 ns) + CELL(0.292 ns) = 9.274 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[74\]~1027'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~88 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[74]~1027 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 9.939 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_11\|add_sub_cella\[5\]~85 14 COMB LAB_X20_Y6 2 " "Info: 14: + IC(0.223 ns) + CELL(0.442 ns) = 9.939 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_11\|add_sub_cella\[5\]~85'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[74]~1027 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~85 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.599 ns) + CELL(0.292 ns) 10.830 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[81\]~1028 15 COMB LAB_X19_Y6 2 " "Info: 15: + IC(0.599 ns) + CELL(0.292 ns) = 10.830 ns; Loc. = LAB_X19_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[81\]~1028'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.891 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~85 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[81]~1028 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 11.495 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_12\|add_sub_cella\[5\]~85 16 COMB LAB_X19_Y6 3 " "Info: 16: + IC(0.223 ns) + CELL(0.442 ns) = 11.495 ns; Loc. = LAB_X19_Y6; Fanout = 3; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_12\|add_sub_cella\[5\]~85'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[81]~1028 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~85 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.442 ns) 12.386 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_14\|add_sub_cella\[5\]~103 17 COMB LAB_X18_Y6 2 " "Info: 17: + IC(0.449 ns) + CELL(0.442 ns) = 12.386 ns; Loc. = LAB_X18_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_14\|add_sub_cella\[5\]~103'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.891 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~85 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~103 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 13.051 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[95\]~1029 18 COMB LAB_X18_Y6 3 " "Info: 18: + IC(0.223 ns) + CELL(0.442 ns) = 13.051 ns; Loc. = LAB_X18_Y6; Fanout = 3; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|StageOut\[95\]~1029'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~103 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~1029 } "NODE_NAME" } "" } } { "db/alt_u_div_jod.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/alt_u_div_jod.tdf" 73 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.114 ns) 13.716 ns ddsout_rom~764 19 COMB LAB_X18_Y6 1 " "Info: 19: + IC(0.551 ns) + CELL(0.114 ns) = 13.716 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'ddsout_rom~764'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~1029 ddsout_rom~764 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.114 ns) 14.381 ns mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_14\|add_sub_cella\[5\]~104 20 COMB LAB_X18_Y6 2 " "Info: 20: + IC(0.551 ns) + CELL(0.114 ns) = 14.381 ns; Loc. = LAB_X18_Y6; Fanout = 2; COMB Node = 'mul_6:mul\|ll:u2\|lpm_divide:lpm_divide_component\|lpm_divide_k5j:auto_generated\|sign_div_unsign_7jg:divider\|alt_u_div_jod:divider\|add_sub_qe8:add_sub_14\|add_sub_cella\[5\]~104'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { ddsout_rom~764 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~104 } "NODE_NAME" } "" } } { "db/add_sub_qe8.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/add_sub_qe8.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.114 ns) 15.046 ns ddsout_rom~765 21 COMB LAB_X18_Y6 1 " "Info: 21: + IC(0.551 ns) + CELL(0.114 ns) = 15.046 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'ddsout_rom~765'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.665 ns" { mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~104 ddsout_rom~765 } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.075 ns) + CELL(0.738 ns) 15.859 ns ddsout_rom\[0\] 22 REG LAB_X18_Y6 2 " "Info: 22: + IC(0.075 ns) + CELL(0.738 ns) = 15.859 ns; Loc. = LAB_X18_Y6; Fanout = 2; REG Node = 'ddsout_rom\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "0.813 ns" { ddsout_rom~765 ddsout_rom[0] } "NODE_NAME" } "" } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.293 ns ( 52.29 % ) " "Info: Total cell delay = 8.293 ns ( 52.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.566 ns ( 47.71 % ) " "Info: Total interconnect delay = 7.566 ns ( 47.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "15.859 ns" { mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14] mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~COUTCOUT1_79 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~75 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[39]~1021 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1022 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1023 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~142 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[53]~1024 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~186 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~86 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[67]~1025 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~88 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[74]~1027 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~85 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[81]~1028 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~85 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~103 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~1029 ddsout_rom~764 mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~104 ddsout_rom~765 ddsout_rom[0] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}