dds_sin.map.eqn

用vhdl编写的程序

--A1L68 is ddsout_rom~764
--operation mode is normal

A1L68 = !NB5L4 & !FB1L10;


--NB5L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~104
--operation mode is normal

NB5L7 = NB4L4 & FB1L9 # !NB4L4 & !FB1L9 & NB4L6 # !A1L68;


--A1L69 is ddsout_rom~765
--operation mode is normal

A1L69 = A1L59 & (NB5L7 & A1L67 # !NB5L7 & (T1_dataout_n[5]));


--T1_dataout_n[4] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[4]
--operation mode is arithmetic

T1_dataout_n[4]_carry_eqn = T1L4;
T1_dataout_n[4]_lut_out = X2_result[4] $ X1_result[4] $ !T1_dataout_n[4]_carry_eqn;
T1_dataout_n[4] = DFFEAS(T1_dataout_n[4]_lut_out, sysclk, VCC, , , , , , );

--T1L3 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[4]~167
--operation mode is arithmetic

T1L3 = CARRY(X2_result[4] & (X1_result[4] # !T1L4) # !X2_result[4] & X1_result[4] & !T1L4);


--J1_q_a[0] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_clock_0 = PB1__clk0;
J1_q_a[0]_PORT_A_data_out = MEMORY(, , J1_q_a[0]_PORT_A_address_reg, , , , , , J1_q_a[0]_clock_0, , , , , );
J1_q_a[0] = J1_q_a[0]_PORT_A_data_out[0];


--B1L132 is ddsc:i_dds|add~1281
--operation mode is arithmetic

B1L132_carry_eqn = B1L152;
B1L132 = M1_q_a[1] $ J1_q_a[1] $ B1L132_carry_eqn;

--B1L133 is ddsc:i_dds|add~1283
--operation mode is arithmetic

B1L133 = CARRY(M1_q_a[1] & !J1_q_a[1] & !B1L152 # !M1_q_a[1] & (!B1L152 # !J1_q_a[1]));


--L1_q_a[0] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = PB1__clk0;
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
L1_q_a[0] = L1_q_a[0]_PORT_A_data_out[0];


--A1L70 is ddsout_rom~766
--operation mode is normal

A1L70 = sselect[0] & (B1L132 # !sselect[1]) # !sselect[0] & sselect[1] & (L1_q_a[0]);


--K1_q_a[0] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[0]_PORT_A_address_reg = DFFE(K1_q_a[0]_PORT_A_address, K1_q_a[0]_clock_0, , , );
K1_q_a[0]_clock_0 = PB1__clk0;
K1_q_a[0]_PORT_A_data_out = MEMORY(, , K1_q_a[0]_PORT_A_address_reg, , , , , , K1_q_a[0]_clock_0, , , , , );
K1_q_a[0] = K1_q_a[0]_PORT_A_data_out[0];


--A1L71 is ddsout_rom~767
--operation mode is normal

A1L71 = sselect[1] & (A1L70) # !sselect[1] & (A1L70 & (K1_q_a[0]) # !A1L70 & J1_q_a[0]);


--A1L72 is ddsout_rom~768
--operation mode is normal

A1L72 = A1L59 & T1_dataout_n[4] # !A1L59 & (A1L71);


--A1L73 is ddsout_rom~769
--operation mode is normal

A1L73 = NB5L4 & cmp_sel & sselect[0] & sselect[1];


--L1_q_a[1] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = PB1__clk0;
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
L1_q_a[1] = L1_q_a[1]_PORT_A_data_out[0];


--A1L60 is ddsout_rom[3]~771
--operation mode is normal

A1L60 = sselect[0] $ sselect[1];


--B1L134 is ddsc:i_dds|add~1286
--operation mode is arithmetic

B1L134_carry_eqn = B1L133;
B1L134 = M1_q_a[2] $ J1_q_a[2] $ !B1L134_carry_eqn;

--B1L135 is ddsc:i_dds|add~1288
--operation mode is arithmetic

B1L135 = CARRY(M1_q_a[2] & (J1_q_a[2] # !B1L133) # !M1_q_a[2] & J1_q_a[2] & !B1L133);


--J1_q_a[1] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[1]_PORT_A_address_reg = DFFE(J1_q_a[1]_PORT_A_address, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_clock_0 = PB1__clk0;
J1_q_a[1]_PORT_A_data_out = MEMORY(, , J1_q_a[1]_PORT_A_address_reg, , , , , , J1_q_a[1]_clock_0, , , , , );
J1_q_a[1] = J1_q_a[1]_PORT_A_data_out[0];


--A1L74 is ddsout_rom~772
--operation mode is normal

A1L74 = sselect[0] & (B1L134 # !sselect[1]) # !sselect[0] & !sselect[1] & (J1_q_a[1]);


--K1_q_a[1] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , );
K1_q_a[1]_clock_0 = PB1__clk0;
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , , , , );
K1_q_a[1] = K1_q_a[1]_PORT_A_data_out[0];


--A1L75 is ddsout_rom~773
--operation mode is normal

A1L75 = A1L60 & (A1L74 & (K1_q_a[1]) # !A1L74 & L1_q_a[1]) # !A1L60 & (A1L74);


--J1_q_a[2] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[2]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[2]_PORT_A_address_reg = DFFE(J1_q_a[2]_PORT_A_address, J1_q_a[2]_clock_0, , , );
J1_q_a[2]_clock_0 = PB1__clk0;
J1_q_a[2]_PORT_A_data_out = MEMORY(, , J1_q_a[2]_PORT_A_address_reg, , , , , , J1_q_a[2]_clock_0, , , , , );
J1_q_a[2] = J1_q_a[2]_PORT_A_data_out[0];


--B1L136 is ddsc:i_dds|add~1291
--operation mode is arithmetic

B1L136_carry_eqn = B1L135;
B1L136 = M1_q_a[3] $ J1_q_a[3] $ B1L136_carry_eqn;

--B1L137 is ddsc:i_dds|add~1293
--operation mode is arithmetic

B1L137 = CARRY(M1_q_a[3] & !J1_q_a[3] & !B1L135 # !M1_q_a[3] & (!B1L135 # !J1_q_a[3]));


--L1_q_a[2] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[2]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[2]_PORT_A_address_reg = DFFE(L1_q_a[2]_PORT_A_address, L1_q_a[2]_clock_0, , , );
L1_q_a[2]_clock_0 = PB1__clk0;
L1_q_a[2]_PORT_A_data_out = MEMORY(, , L1_q_a[2]_PORT_A_address_reg, , , , , , L1_q_a[2]_clock_0, , , , , );
L1_q_a[2] = L1_q_a[2]_PORT_A_data_out[0];


--A1L76 is ddsout_rom~775
--operation mode is normal

A1L76 = sselect[0] & (B1L136 # !sselect[1]) # !sselect[0] & sselect[1] & (L1_q_a[2]);


--K1_q_a[2] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[2]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[2]_PORT_A_address_reg = DFFE(K1_q_a[2]_PORT_A_address, K1_q_a[2]_clock_0, , , );
K1_q_a[2]_clock_0 = PB1__clk0;
K1_q_a[2]_PORT_A_data_out = MEMORY(, , K1_q_a[2]_PORT_A_address_reg, , , , , , K1_q_a[2]_clock_0, , , , , );
K1_q_a[2] = K1_q_a[2]_PORT_A_data_out[0];


--A1L77 is ddsout_rom~776
--operation mode is normal

A1L77 = sselect[1] & (A1L76) # !sselect[1] & (A1L76 & (K1_q_a[2]) # !A1L76 & J1_q_a[2]);


--L1_q_a[3] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[3]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[3]_PORT_A_address_reg = DFFE(L1_q_a[3]_PORT_A_address, L1_q_a[3]_clock_0, , , );
L1_q_a[3]_clock_0 = PB1__clk0;
L1_q_a[3]_PORT_A_data_out = MEMORY(, , L1_q_a[3]_PORT_A_address_reg, , , , , , L1_q_a[3]_clock_0, , , , , );
L1_q_a[3] = L1_q_a[3]_PORT_A_data_out[0];


--B1L138 is ddsc:i_dds|add~1296
--operation mode is arithmetic

B1L138_carry_eqn = B1L137;
B1L138 = M1_q_a[4] $ J1_q_a[4] $ !B1L138_carry_eqn;

--B1L139 is ddsc:i_dds|add~1298
--operation mode is arithmetic

B1L139 = CARRY(M1_q_a[4] & (J1_q_a[4] # !B1L137) # !M1_q_a[4] & J1_q_a[4] & !B1L137);


--J1_q_a[3] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[3]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[3]_PORT_A_address_reg = DFFE(J1_q_a[3]_PORT_A_address, J1_q_a[3]_clock_0, , , );
J1_q_a[3]_clock_0 = PB1__clk0;
J1_q_a[3]_PORT_A_data_out = MEMORY(, , J1_q_a[3]_PORT_A_address_reg, , , , , , J1_q_a[3]_clock_0, , , , , );
J1_q_a[3] = J1_q_a[3]_PORT_A_data_out[0];


--A1L78 is ddsout_rom~778
--operation mode is normal

A1L78 = sselect[0] & (B1L138 # !sselect[1]) # !sselect[0] & !sselect[1] & (J1_q_a[3]);