dds_sin.map.eqn

用vhdl编写的程序

QB1_q_b[8]_PORT_B_read_enable = VCC;
QB1_q_b[8]_PORT_B_read_enable_reg = DFFE(QB1_q_b[8]_PORT_B_read_enable, QB1_q_b[8]_clock_1, , , );
QB1_q_b[8]_clock_0 = sysclk;
QB1_q_b[8]_clock_1 = sysclk;
QB1_q_b[8]_PORT_B_data_out = MEMORY(QB1_q_b[8]_PORT_A_data_in_reg, , QB1_q_b[8]_PORT_A_address_reg, QB1_q_b[8]_PORT_B_address_reg, QB1_q_b[8]_PORT_A_write_enable_reg, QB1_q_b[8]_PORT_B_read_enable_reg, , , QB1_q_b[8]_clock_0, QB1_q_b[8]_clock_1, , , , );
QB1_q_b[8]_PORT_B_data_out_reg = DFFE(QB1_q_b[8]_PORT_B_data_out, QB1_q_b[8]_clock_1, , , );
QB1_q_b[8] = QB1_q_b[8]_PORT_B_data_out_reg[0];


--QB1_q_b[9] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[9]_PORT_A_data_in = DIN[9];
QB1_q_b[9]_PORT_A_data_in_reg = DFFE(QB1_q_b[9]_PORT_A_data_in, QB1_q_b[9]_clock_0, , , );
QB1_q_b[9]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[9]_PORT_A_address_reg = DFFE(QB1_q_b[9]_PORT_A_address, QB1_q_b[9]_clock_0, , , );
QB1_q_b[9]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[9]_PORT_B_address_reg = DFFE(QB1_q_b[9]_PORT_B_address, QB1_q_b[9]_clock_1, , , );
QB1_q_b[9]_PORT_A_write_enable = VCC;
QB1_q_b[9]_PORT_A_write_enable_reg = DFFE(QB1_q_b[9]_PORT_A_write_enable, QB1_q_b[9]_clock_0, , , );
QB1_q_b[9]_PORT_B_read_enable = VCC;
QB1_q_b[9]_PORT_B_read_enable_reg = DFFE(QB1_q_b[9]_PORT_B_read_enable, QB1_q_b[9]_clock_1, , , );
QB1_q_b[9]_clock_0 = sysclk;
QB1_q_b[9]_clock_1 = sysclk;
QB1_q_b[9]_PORT_B_data_out = MEMORY(QB1_q_b[9]_PORT_A_data_in_reg, , QB1_q_b[9]_PORT_A_address_reg, QB1_q_b[9]_PORT_B_address_reg, QB1_q_b[9]_PORT_A_write_enable_reg, QB1_q_b[9]_PORT_B_read_enable_reg, , , QB1_q_b[9]_clock_0, QB1_q_b[9]_clock_1, , , , );
QB1_q_b[9]_PORT_B_data_out_reg = DFFE(QB1_q_b[9]_PORT_B_data_out, QB1_q_b[9]_clock_1, , , );
QB1_q_b[9] = QB1_q_b[9]_PORT_B_data_out_reg[0];


--count[0] is count[0]
--operation mode is arithmetic

count[0]_lut_out = !count[0];
count[0] = DFFEAS(count[0]_lut_out, amp, VCC, , , , , , );

--A1L17 is count[0]~57
--operation mode is arithmetic

A1L17 = CARRY(count[0]);


--count[1] is count[1]
--operation mode is arithmetic

count[1]_carry_eqn = A1L17;
count[1]_lut_out = count[1] $ (count[1]_carry_eqn);
count[1] = DFFEAS(count[1]_lut_out, amp, VCC, , , , , , );

--A1L19 is count[1]~61
--operation mode is arithmetic

A1L19 = CARRY(!A1L17 # !count[1]);


--count[2] is count[2]
--operation mode is arithmetic

count[2]_carry_eqn = A1L19;
count[2]_lut_out = count[2] $ (count[2]_carry_eqn);
count[2] = DFFEAS(count[2]_lut_out, amp, VCC, , , , , , );

--A1L21 is count[2]~65
--operation mode is arithmetic

A1L21 = CARRY(count[2] # !A1L19);


--count[3] is count[3]
--operation mode is arithmetic

count[3]_carry_eqn = A1L21;
count[3]_lut_out = count[3] $ (count[3]_carry_eqn);
count[3] = DFFEAS(count[3]_lut_out, amp, VCC, , , , , , );

--A1L23 is count[3]~69
--operation mode is arithmetic

A1L23 = CARRY(!A1L21 # !count[3]);


--count[4] is count[4]
--operation mode is arithmetic

count[4]_carry_eqn = A1L23;
count[4]_lut_out = count[4] $ (!count[4]_carry_eqn);
count[4] = DFFEAS(count[4]_lut_out, amp, VCC, , , , , , );

--A1L25 is count[4]~73
--operation mode is arithmetic

A1L25 = CARRY(count[4] & (!A1L23));


--count[5] is count[5]
--operation mode is arithmetic

count[5]_carry_eqn = A1L25;
count[5]_lut_out = count[5] $ (count[5]_carry_eqn);
count[5] = DFFEAS(count[5]_lut_out, amp, VCC, , , , , , );

--A1L27 is count[5]~77
--operation mode is arithmetic

A1L27 = CARRY(!A1L25 # !count[5]);


--count[6] is count[6]
--operation mode is arithmetic

count[6]_carry_eqn = A1L27;
count[6]_lut_out = count[6] $ (!count[6]_carry_eqn);
count[6] = DFFEAS(count[6]_lut_out, amp, VCC, , , , , , );

--A1L29 is count[6]~81
--operation mode is arithmetic

A1L29 = CARRY(count[6] & (!A1L27));


--count[7] is count[7]
--operation mode is normal

count[7]_carry_eqn = A1L29;
count[7]_lut_out = count[7] $ (count[7]_carry_eqn);
count[7] = DFFEAS(count[7]_lut_out, amp, VCC, , , , , , );


--A1L59 is ddsout_rom[3]~762
--operation mode is normal

A1L59 = cmp_sel & sselect[0] & sselect[1];


--NB5_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[4]
--operation mode is arithmetic

NB5_add_sub_cella[4] = T1_dataout_n[5];

--NB5L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB5L5 = CARRY(T1_dataout_n[5]);


--T1_dataout_n[6] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[6]
--operation mode is arithmetic

T1_dataout_n[6]_carry_eqn = T1L9;
T1_dataout_n[6]_lut_out = X2_result[6] $ X1_result[6] $ !T1_dataout_n[6]_carry_eqn;
T1_dataout_n[6] = DFFEAS(T1_dataout_n[6]_lut_out, sysclk, VCC, , , , , , );

--T1L11 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[6]~123
--operation mode is arithmetic

T1L11 = CARRY(X2_result[6] & (X1_result[6] # !T1L9) # !X2_result[6] & X1_result[6] & !T1L9);


--NB3_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]
--operation mode is arithmetic

NB3_add_sub_cella[4] = T1_dataout_n[7];

--NB3L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB3L5 = CARRY(T1_dataout_n[7]);


--T1_dataout_n[8] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]
--operation mode is arithmetic

T1_dataout_n[8]_carry_eqn = T1L13;
T1_dataout_n[8]_lut_out = X2_result[8] $ X1_result[8] $ !T1_dataout_n[8]_carry_eqn;
T1_dataout_n[8] = DFFEAS(T1_dataout_n[8]_lut_out, sysclk, VCC, , , , , , );

--T1L15 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[8]~127
--operation mode is arithmetic

T1L15 = CARRY(X2_result[8] & (X1_result[8] # !T1L13) # !X2_result[8] & X1_result[8] & !T1L13);


--NB2_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[4]
--operation mode is arithmetic

NB2_add_sub_cella[4] = T1_dataout_n[8];

--NB2L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB2L5 = CARRY(T1_dataout_n[8]);


--T1_dataout_n[9] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[9]
--operation mode is arithmetic

T1_dataout_n[9]_carry_eqn = T1L15;
T1_dataout_n[9]_lut_out = X2_result[9] $ X1_result[9] $ T1_dataout_n[9]_carry_eqn;
T1_dataout_n[9] = DFFEAS(T1_dataout_n[9]_lut_out, sysclk, VCC, , , , , , );

--T1L17 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[9]~131
--operation mode is arithmetic

T1L17 = CARRY(X2_result[9] & !X1_result[9] & !T1L15 # !X2_result[9] & (!T1L15 # !X1_result[9]));


--NB1_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[4]
--operation mode is arithmetic

NB1_add_sub_cella[4] = T1_dataout_n[9];

--NB1L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB1L5 = CARRY(T1_dataout_n[9]);


--T1_dataout_n[10] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[10]
--operation mode is arithmetic

T1_dataout_n[10]_carry_eqn = T1L17;
T1_dataout_n[10]_lut_out = X2_result[10] $ X1_result[10] $ !T1_dataout_n[10]_carry_eqn;
T1_dataout_n[10] = DFFEAS(T1_dataout_n[10]_lut_out, sysclk, VCC, , , , , , );

--T1L19 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[10]~135
--operation mode is arithmetic

T1L19 = CARRY(X2_result[10] & (X1_result[10] # !T1L17) # !X2_result[10] & X1_result[10] & !T1L17);


--NB9_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[4]
--operation mode is arithmetic

NB9_add_sub_cella[4] = T1_dataout_n[11];

--NB9L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB9L5 = CARRY(T1_dataout_n[11]);


--T1_dataout_n[12] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[12]
--operation mode is arithmetic

T1_dataout_n[12]_carry_eqn = T1L21;
T1_dataout_n[12]_lut_out = X2_result[12] $ X1_result[12] $ !T1_dataout_n[12]_carry_eqn;
T1_dataout_n[12] = DFFEAS(T1_dataout_n[12]_lut_out, sysclk, VCC, , , , , , );

--T1L23 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[12]~139
--operation mode is arithmetic

T1L23 = CARRY(X2_result[12] & (X1_result[12] # !T1L21) # !X2_result[12] & X1_result[12] & !T1L21);


--NB8_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[4]
--operation mode is arithmetic

NB8_add_sub_cella[4] = T1_dataout_n[12];

--NB8L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB8L5 = CARRY(T1_dataout_n[12]);


--T1_dataout_n[13] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[13]
--operation mode is arithmetic

T1_dataout_n[13]_carry_eqn = T1L23;
T1_dataout_n[13]_lut_out = X2_result[13] $ X1_result[13] $ T1_dataout_n[13]_carry_eqn;
T1_dataout_n[13] = DFFEAS(T1_dataout_n[13]_lut_out, sysclk, VCC, , , , , , );