dds_sin.map.eqn

用vhdl编写的程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--ddsout_rom[0] is ddsout_rom[0]
--operation mode is normal

ddsout_rom[0]_lut_out = A1L69 # A1L72 # FB1L10 & A1L73;
ddsout_rom[0] = DFFEAS(ddsout_rom[0]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[1] is ddsout_rom[1]
--operation mode is normal

ddsout_rom[1]_lut_out = A1L59 & NB5L7 # !A1L59 & (A1L75);
ddsout_rom[1] = DFFEAS(ddsout_rom[1]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[2] is ddsout_rom[2]
--operation mode is normal

ddsout_rom[2]_lut_out = A1L59 & (NB4L6 # !NB5L6) # !A1L59 & (A1L77);
ddsout_rom[2] = DFFEAS(ddsout_rom[2]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[3] is ddsout_rom[3]
--operation mode is normal

ddsout_rom[3]_lut_out = A1L59 & NB3L7 # !A1L59 & (A1L79);
ddsout_rom[3] = DFFEAS(ddsout_rom[3]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[4] is ddsout_rom[4]
--operation mode is normal

ddsout_rom[4]_lut_out = A1L59 & NB2L7 # !A1L59 & (A1L81);
ddsout_rom[4] = DFFEAS(ddsout_rom[4]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[5] is ddsout_rom[5]
--operation mode is normal

ddsout_rom[5]_lut_out = A1L59 & NB1L8 # !A1L59 & (A1L83);
ddsout_rom[5] = DFFEAS(ddsout_rom[5]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[6] is ddsout_rom[6]
--operation mode is normal

ddsout_rom[6]_lut_out = A1L59 & (NB10L6 # !NB1L6) # !A1L59 & (A1L85);
ddsout_rom[6] = DFFEAS(ddsout_rom[6]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[7] is ddsout_rom[7]
--operation mode is normal

ddsout_rom[7]_lut_out = A1L59 & NB9L7 # !A1L59 & (A1L87);
ddsout_rom[7] = DFFEAS(ddsout_rom[7]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[8] is ddsout_rom[8]
--operation mode is normal

ddsout_rom[8]_lut_out = A1L59 & NB8L7 # !A1L59 & (A1L89);
ddsout_rom[8] = DFFEAS(ddsout_rom[8]_lut_out, !sysclk, VCC, , , , , , );


--ddsout_rom[9] is ddsout_rom[9]
--operation mode is normal

ddsout_rom[9]_lut_out = A1L59 & FB1L2 # !A1L59 & (A1L91);
ddsout_rom[9] = DFFEAS(ddsout_rom[9]_lut_out, !sysclk, VCC, , , , , , );


--QB1_q_b[0] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[0]_PORT_A_data_in = DIN[0];
QB1_q_b[0]_PORT_A_data_in_reg = DFFE(QB1_q_b[0]_PORT_A_data_in, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[0]_PORT_A_address_reg = DFFE(QB1_q_b[0]_PORT_A_address, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[0]_PORT_B_address_reg = DFFE(QB1_q_b[0]_PORT_B_address, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_PORT_A_write_enable = VCC;
QB1_q_b[0]_PORT_A_write_enable_reg = DFFE(QB1_q_b[0]_PORT_A_write_enable, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_read_enable = VCC;
QB1_q_b[0]_PORT_B_read_enable_reg = DFFE(QB1_q_b[0]_PORT_B_read_enable, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_clock_0 = sysclk;
QB1_q_b[0]_clock_1 = sysclk;
QB1_q_b[0]_PORT_B_data_out = MEMORY(QB1_q_b[0]_PORT_A_data_in_reg, , QB1_q_b[0]_PORT_A_address_reg, QB1_q_b[0]_PORT_B_address_reg, QB1_q_b[0]_PORT_A_write_enable_reg, QB1_q_b[0]_PORT_B_read_enable_reg, , , QB1_q_b[0]_clock_0, QB1_q_b[0]_clock_1, , , , );
QB1_q_b[0]_PORT_B_data_out_reg = DFFE(QB1_q_b[0]_PORT_B_data_out, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0] = QB1_q_b[0]_PORT_B_data_out_reg[0];


--QB1_q_b[1] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[1]_PORT_A_data_in = DIN[1];
QB1_q_b[1]_PORT_A_data_in_reg = DFFE(QB1_q_b[1]_PORT_A_data_in, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[1]_PORT_A_address_reg = DFFE(QB1_q_b[1]_PORT_A_address, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[1]_PORT_B_address_reg = DFFE(QB1_q_b[1]_PORT_B_address, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1]_PORT_A_write_enable = VCC;
QB1_q_b[1]_PORT_A_write_enable_reg = DFFE(QB1_q_b[1]_PORT_A_write_enable, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_B_read_enable = VCC;
QB1_q_b[1]_PORT_B_read_enable_reg = DFFE(QB1_q_b[1]_PORT_B_read_enable, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1]_clock_0 = sysclk;
QB1_q_b[1]_clock_1 = sysclk;
QB1_q_b[1]_PORT_B_data_out = MEMORY(QB1_q_b[1]_PORT_A_data_in_reg, , QB1_q_b[1]_PORT_A_address_reg, QB1_q_b[1]_PORT_B_address_reg, QB1_q_b[1]_PORT_A_write_enable_reg, QB1_q_b[1]_PORT_B_read_enable_reg, , , QB1_q_b[1]_clock_0, QB1_q_b[1]_clock_1, , , , );
QB1_q_b[1]_PORT_B_data_out_reg = DFFE(QB1_q_b[1]_PORT_B_data_out, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1] = QB1_q_b[1]_PORT_B_data_out_reg[0];


--QB1_q_b[2] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[2]_PORT_A_data_in = DIN[2];
QB1_q_b[2]_PORT_A_data_in_reg = DFFE(QB1_q_b[2]_PORT_A_data_in, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[2]_PORT_A_address_reg = DFFE(QB1_q_b[2]_PORT_A_address, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[2]_PORT_B_address_reg = DFFE(QB1_q_b[2]_PORT_B_address, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_PORT_A_write_enable = VCC;
QB1_q_b[2]_PORT_A_write_enable_reg = DFFE(QB1_q_b[2]_PORT_A_write_enable, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_read_enable = VCC;
QB1_q_b[2]_PORT_B_read_enable_reg = DFFE(QB1_q_b[2]_PORT_B_read_enable, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_clock_0 = sysclk;
QB1_q_b[2]_clock_1 = sysclk;
QB1_q_b[2]_PORT_B_data_out = MEMORY(QB1_q_b[2]_PORT_A_data_in_reg, , QB1_q_b[2]_PORT_A_address_reg, QB1_q_b[2]_PORT_B_address_reg, QB1_q_b[2]_PORT_A_write_enable_reg, QB1_q_b[2]_PORT_B_read_enable_reg, , , QB1_q_b[2]_clock_0, QB1_q_b[2]_clock_1, , , , );
QB1_q_b[2]_PORT_B_data_out_reg = DFFE(QB1_q_b[2]_PORT_B_data_out, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2] = QB1_q_b[2]_PORT_B_data_out_reg[0];


--QB1_q_b[3] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[3]_PORT_A_data_in = DIN[3];
QB1_q_b[3]_PORT_A_data_in_reg = DFFE(QB1_q_b[3]_PORT_A_data_in, QB1_q_b[3]_clock_0, , , );
QB1_q_b[3]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[3]_PORT_A_address_reg = DFFE(QB1_q_b[3]_PORT_A_address, QB1_q_b[3]_clock_0, , , );
QB1_q_b[3]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[3]_PORT_B_address_reg = DFFE(QB1_q_b[3]_PORT_B_address, QB1_q_b[3]_clock_1, , , );
QB1_q_b[3]_PORT_A_write_enable = VCC;
QB1_q_b[3]_PORT_A_write_enable_reg = DFFE(QB1_q_b[3]_PORT_A_write_enable, QB1_q_b[3]_clock_0, , , );
QB1_q_b[3]_PORT_B_read_enable = VCC;
QB1_q_b[3]_PORT_B_read_enable_reg = DFFE(QB1_q_b[3]_PORT_B_read_enable, QB1_q_b[3]_clock_1, , , );
QB1_q_b[3]_clock_0 = sysclk;
QB1_q_b[3]_clock_1 = sysclk;
QB1_q_b[3]_PORT_B_data_out = MEMORY(QB1_q_b[3]_PORT_A_data_in_reg, , QB1_q_b[3]_PORT_A_address_reg, QB1_q_b[3]_PORT_B_address_reg, QB1_q_b[3]_PORT_A_write_enable_reg, QB1_q_b[3]_PORT_B_read_enable_reg, , , QB1_q_b[3]_clock_0, QB1_q_b[3]_clock_1, , , , );
QB1_q_b[3]_PORT_B_data_out_reg = DFFE(QB1_q_b[3]_PORT_B_data_out, QB1_q_b[3]_clock_1, , , );
QB1_q_b[3] = QB1_q_b[3]_PORT_B_data_out_reg[0];


--QB1_q_b[4] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[4]_PORT_A_data_in = DIN[4];
QB1_q_b[4]_PORT_A_data_in_reg = DFFE(QB1_q_b[4]_PORT_A_data_in, QB1_q_b[4]_clock_0, , , );
QB1_q_b[4]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[4]_PORT_A_address_reg = DFFE(QB1_q_b[4]_PORT_A_address, QB1_q_b[4]_clock_0, , , );
QB1_q_b[4]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[4]_PORT_B_address_reg = DFFE(QB1_q_b[4]_PORT_B_address, QB1_q_b[4]_clock_1, , , );
QB1_q_b[4]_PORT_A_write_enable = VCC;
QB1_q_b[4]_PORT_A_write_enable_reg = DFFE(QB1_q_b[4]_PORT_A_write_enable, QB1_q_b[4]_clock_0, , , );
QB1_q_b[4]_PORT_B_read_enable = VCC;
QB1_q_b[4]_PORT_B_read_enable_reg = DFFE(QB1_q_b[4]_PORT_B_read_enable, QB1_q_b[4]_clock_1, , , );
QB1_q_b[4]_clock_0 = sysclk;
QB1_q_b[4]_clock_1 = sysclk;
QB1_q_b[4]_PORT_B_data_out = MEMORY(QB1_q_b[4]_PORT_A_data_in_reg, , QB1_q_b[4]_PORT_A_address_reg, QB1_q_b[4]_PORT_B_address_reg, QB1_q_b[4]_PORT_A_write_enable_reg, QB1_q_b[4]_PORT_B_read_enable_reg, , , QB1_q_b[4]_clock_0, QB1_q_b[4]_clock_1, , , , );
QB1_q_b[4]_PORT_B_data_out_reg = DFFE(QB1_q_b[4]_PORT_B_data_out, QB1_q_b[4]_clock_1, , , );
QB1_q_b[4] = QB1_q_b[4]_PORT_B_data_out_reg[0];


--QB1_q_b[5] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[5]_PORT_A_data_in = DIN[5];
QB1_q_b[5]_PORT_A_data_in_reg = DFFE(QB1_q_b[5]_PORT_A_data_in, QB1_q_b[5]_clock_0, , , );
QB1_q_b[5]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[5]_PORT_A_address_reg = DFFE(QB1_q_b[5]_PORT_A_address, QB1_q_b[5]_clock_0, , , );
QB1_q_b[5]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[5]_PORT_B_address_reg = DFFE(QB1_q_b[5]_PORT_B_address, QB1_q_b[5]_clock_1, , , );
QB1_q_b[5]_PORT_A_write_enable = VCC;
QB1_q_b[5]_PORT_A_write_enable_reg = DFFE(QB1_q_b[5]_PORT_A_write_enable, QB1_q_b[5]_clock_0, , , );
QB1_q_b[5]_PORT_B_read_enable = VCC;
QB1_q_b[5]_PORT_B_read_enable_reg = DFFE(QB1_q_b[5]_PORT_B_read_enable, QB1_q_b[5]_clock_1, , , );
QB1_q_b[5]_clock_0 = sysclk;
QB1_q_b[5]_clock_1 = sysclk;
QB1_q_b[5]_PORT_B_data_out = MEMORY(QB1_q_b[5]_PORT_A_data_in_reg, , QB1_q_b[5]_PORT_A_address_reg, QB1_q_b[5]_PORT_B_address_reg, QB1_q_b[5]_PORT_A_write_enable_reg, QB1_q_b[5]_PORT_B_read_enable_reg, , , QB1_q_b[5]_clock_0, QB1_q_b[5]_clock_1, , , , );
QB1_q_b[5]_PORT_B_data_out_reg = DFFE(QB1_q_b[5]_PORT_B_data_out, QB1_q_b[5]_clock_1, , , );
QB1_q_b[5] = QB1_q_b[5]_PORT_B_data_out_reg[0];


--QB1_q_b[6] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[6]_PORT_A_data_in = DIN[6];
QB1_q_b[6]_PORT_A_data_in_reg = DFFE(QB1_q_b[6]_PORT_A_data_in, QB1_q_b[6]_clock_0, , , );
QB1_q_b[6]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[6]_PORT_A_address_reg = DFFE(QB1_q_b[6]_PORT_A_address, QB1_q_b[6]_clock_0, , , );
QB1_q_b[6]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[6]_PORT_B_address_reg = DFFE(QB1_q_b[6]_PORT_B_address, QB1_q_b[6]_clock_1, , , );
QB1_q_b[6]_PORT_A_write_enable = VCC;
QB1_q_b[6]_PORT_A_write_enable_reg = DFFE(QB1_q_b[6]_PORT_A_write_enable, QB1_q_b[6]_clock_0, , , );
QB1_q_b[6]_PORT_B_read_enable = VCC;
QB1_q_b[6]_PORT_B_read_enable_reg = DFFE(QB1_q_b[6]_PORT_B_read_enable, QB1_q_b[6]_clock_1, , , );
QB1_q_b[6]_clock_0 = sysclk;
QB1_q_b[6]_clock_1 = sysclk;
QB1_q_b[6]_PORT_B_data_out = MEMORY(QB1_q_b[6]_PORT_A_data_in_reg, , QB1_q_b[6]_PORT_A_address_reg, QB1_q_b[6]_PORT_B_address_reg, QB1_q_b[6]_PORT_A_write_enable_reg, QB1_q_b[6]_PORT_B_read_enable_reg, , , QB1_q_b[6]_clock_0, QB1_q_b[6]_clock_1, , , , );
QB1_q_b[6]_PORT_B_data_out_reg = DFFE(QB1_q_b[6]_PORT_B_data_out, QB1_q_b[6]_clock_1, , , );
QB1_q_b[6] = QB1_q_b[6]_PORT_B_data_out_reg[0];


--QB1_q_b[7] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[7]_PORT_A_data_in = DIN[7];
QB1_q_b[7]_PORT_A_data_in_reg = DFFE(QB1_q_b[7]_PORT_A_data_in, QB1_q_b[7]_clock_0, , , );
QB1_q_b[7]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[7]_PORT_A_address_reg = DFFE(QB1_q_b[7]_PORT_A_address, QB1_q_b[7]_clock_0, , , );
QB1_q_b[7]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[7]_PORT_B_address_reg = DFFE(QB1_q_b[7]_PORT_B_address, QB1_q_b[7]_clock_1, , , );
QB1_q_b[7]_PORT_A_write_enable = VCC;
QB1_q_b[7]_PORT_A_write_enable_reg = DFFE(QB1_q_b[7]_PORT_A_write_enable, QB1_q_b[7]_clock_0, , , );
QB1_q_b[7]_PORT_B_read_enable = VCC;
QB1_q_b[7]_PORT_B_read_enable_reg = DFFE(QB1_q_b[7]_PORT_B_read_enable, QB1_q_b[7]_clock_1, , , );
QB1_q_b[7]_clock_0 = sysclk;
QB1_q_b[7]_clock_1 = sysclk;
QB1_q_b[7]_PORT_B_data_out = MEMORY(QB1_q_b[7]_PORT_A_data_in_reg, , QB1_q_b[7]_PORT_A_address_reg, QB1_q_b[7]_PORT_B_address_reg, QB1_q_b[7]_PORT_A_write_enable_reg, QB1_q_b[7]_PORT_B_read_enable_reg, , , QB1_q_b[7]_clock_0, QB1_q_b[7]_clock_1, , , , );
QB1_q_b[7]_PORT_B_data_out_reg = DFFE(QB1_q_b[7]_PORT_B_data_out, QB1_q_b[7]_clock_1, , , );
QB1_q_b[7] = QB1_q_b[7]_PORT_B_data_out_reg[0];


--QB1_q_b[8] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[8]_PORT_A_data_in = DIN[8];
QB1_q_b[8]_PORT_A_data_in_reg = DFFE(QB1_q_b[8]_PORT_A_data_in, QB1_q_b[8]_clock_0, , , );
QB1_q_b[8]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[8]_PORT_A_address_reg = DFFE(QB1_q_b[8]_PORT_A_address, QB1_q_b[8]_clock_0, , , );
QB1_q_b[8]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[8]_PORT_B_address_reg = DFFE(QB1_q_b[8]_PORT_B_address, QB1_q_b[8]_clock_1, , , );
QB1_q_b[8]_PORT_A_write_enable = VCC;
QB1_q_b[8]_PORT_A_write_enable_reg = DFFE(QB1_q_b[8]_PORT_A_write_enable, QB1_q_b[8]_clock_0, , , );