dds_sin.fit.eqn

用vhdl编写的程序

J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[0]_PORT_A_data_out = MEMORY(, , J1_q_a[0]_PORT_A_address_reg, , , , , , J1_q_a[0]_clock_0, , , , , );
J1_q_a[6] = J1_q_a[0]_PORT_A_data_out[3];

--K1_q_a[2] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[2] at M4K_X13_Y8
J1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[0]_PORT_A_data_out = MEMORY(, , J1_q_a[0]_PORT_A_address_reg, , , , , , J1_q_a[0]_clock_0, , , , , );
K1_q_a[2] = J1_q_a[0]_PORT_A_data_out[2];

--J1_q_a[2] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[2] at M4K_X13_Y8
J1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[0]_PORT_A_data_out = MEMORY(, , J1_q_a[0]_PORT_A_address_reg, , , , , , J1_q_a[0]_clock_0, , , , , );
J1_q_a[2] = J1_q_a[0]_PORT_A_data_out[1];


--B1L180 is ddsc:i_dds|add~1281 at LC_X15_Y6_N6
--operation mode is arithmetic

B1L180 = J1_q_a[1] $ M1_q_a[1] $ B1L207;

--B1L181 is ddsc:i_dds|add~1283 at LC_X15_Y6_N6
--operation mode is arithmetic

B1L181_cout_0 = J1_q_a[1] & !M1_q_a[1] & !B1L207 # !J1_q_a[1] & (!B1L207 # !M1_q_a[1]);
B1L181 = CARRY(B1L181_cout_0);

--B1L182 is ddsc:i_dds|add~1283COUT1_1348 at LC_X15_Y6_N6
--operation mode is arithmetic

B1L182_cout_1 = J1_q_a[1] & !M1_q_a[1] & !B1L208 # !J1_q_a[1] & (!B1L208 # !M1_q_a[1]);
B1L182 = CARRY(B1L182_cout_1);


--L1_q_a[0] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[0] at M4K_X13_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
L1_q_a[0] = L1_q_a[0]_PORT_A_data_out[0];

--K1_q_a[9] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[9] at M4K_X13_Y11
L1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
K1_q_a[9] = L1_q_a[0]_PORT_A_data_out[3];

--K1_q_a[8] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[8] at M4K_X13_Y11
L1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
K1_q_a[8] = L1_q_a[0]_PORT_A_data_out[2];

--K1_q_a[0] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[0] at M4K_X13_Y11
L1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
K1_q_a[0] = L1_q_a[0]_PORT_A_data_out[1];


--A1L78 is ddsout_rom~766 at LC_X16_Y6_N9
--operation mode is normal

A1L78 = sselect[0] & (B1L180 # !sselect[1]) # !sselect[0] & L1_q_a[0] & sselect[1];


--A1L79 is ddsout_rom~767 at LC_X17_Y6_N2
--operation mode is normal

A1L79 = sselect[1] & (A1L78) # !sselect[1] & (A1L78 & (K1_q_a[0]) # !A1L78 & J1_q_a[0]);


--A1L80 is ddsout_rom~768 at LC_X18_Y6_N8
--operation mode is normal

A1L80 = A1L67 & (T1_dataout_n[4]) # !A1L67 & (A1L79);


--A1L81 is ddsout_rom~769 at LC_X16_Y6_N7
--operation mode is normal

A1L81 = NB5L4 & cmp_sel & sselect[1] & sselect[0];


--L1_q_a[1] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[1] at M4K_X13_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
L1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
L1_q_a[1] = L1_q_a[1]_PORT_A_data_out[0];

--J1_q_a[7] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[7] at M4K_X13_Y7
L1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
J1_q_a[7] = L1_q_a[1]_PORT_A_data_out[3];

--J1_q_a[5] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[5] at M4K_X13_Y7
L1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
J1_q_a[5] = L1_q_a[1]_PORT_A_data_out[2];

--L1_q_a[5] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[5] at M4K_X13_Y7
L1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
L1_q_a[5] = L1_q_a[1]_PORT_A_data_out[1];


--A1L68 is ddsout_rom[3]~771 at LC_X15_Y4_N2
--operation mode is normal

A1L68 = sselect[0] $ sselect[1];


--B1L183 is ddsc:i_dds|add~1286 at LC_X15_Y6_N7
--operation mode is arithmetic

B1L183 = J1_q_a[2] $ M1_q_a[2] $ !B1L181;

--B1L184 is ddsc:i_dds|add~1288 at LC_X15_Y6_N7
--operation mode is arithmetic

B1L184_cout_0 = J1_q_a[2] & (M1_q_a[2] # !B1L181) # !J1_q_a[2] & M1_q_a[2] & !B1L181;
B1L184 = CARRY(B1L184_cout_0);

--B1L185 is ddsc:i_dds|add~1288COUT1_1350 at LC_X15_Y6_N7
--operation mode is arithmetic

B1L185_cout_1 = J1_q_a[2] & (M1_q_a[2] # !B1L182) # !J1_q_a[2] & M1_q_a[2] & !B1L182;
B1L185 = CARRY(B1L185_cout_1);


--J1_q_a[1] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[1] at M4K_X13_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[1]_PORT_A_address_reg = DFFE(J1_q_a[1]_PORT_A_address, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[1]_PORT_A_data_out = MEMORY(, , J1_q_a[1]_PORT_A_address_reg, , , , , , J1_q_a[1]_clock_0, , , , , );
J1_q_a[1] = J1_q_a[1]_PORT_A_data_out[0];

--K1_q_a[4] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[4] at M4K_X13_Y10
J1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[1]_PORT_A_address_reg = DFFE(J1_q_a[1]_PORT_A_address, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[1]_PORT_A_data_out = MEMORY(, , J1_q_a[1]_PORT_A_address_reg, , , , , , J1_q_a[1]_clock_0, , , , , );
K1_q_a[4] = J1_q_a[1]_PORT_A_data_out[3];

--J1_q_a[4] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[4] at M4K_X13_Y10
J1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[1]_PORT_A_address_reg = DFFE(J1_q_a[1]_PORT_A_address, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[1]_PORT_A_data_out = MEMORY(, , J1_q_a[1]_PORT_A_address_reg, , , , , , J1_q_a[1]_clock_0, , , , , );
J1_q_a[4] = J1_q_a[1]_PORT_A_data_out[2];

--J1_q_a[3] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[3] at M4K_X13_Y10
J1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[1]_PORT_A_address_reg = DFFE(J1_q_a[1]_PORT_A_address, J1_q_a[1]_clock_0, , , );
J1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[1]_PORT_A_data_out = MEMORY(, , J1_q_a[1]_PORT_A_address_reg, , , , , , J1_q_a[1]_clock_0, , , , , );
J1_q_a[3] = J1_q_a[1]_PORT_A_data_out[1];


--A1L82 is ddsout_rom~772 at LC_X15_Y6_N1
--operation mode is normal

A1L82 = sselect[0] & (B1L183 # !sselect[1]) # !sselect[0] & !sselect[1] & (J1_q_a[1]);


--K1_q_a[1] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[1] at M4K_X13_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
K1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , );
K1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , , , , );
K1_q_a[1] = K1_q_a[1]_PORT_A_data_out[0];

--K1_q_a[7] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[7] at M4K_X13_Y12
K1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , );
K1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , , , , );
K1_q_a[7] = K1_q_a[1]_PORT_A_data_out[3];

--K1_q_a[5] is ddsc:i_dds|lpm_rom:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated|q_a[5] at M4K_X13_Y12
K1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , );
K1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , , , , );
K1_q_a[5] = K1_q_a[1]_PORT_A_data_out[2];

--L1_q_a[3] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[3] at M4K_X13_Y12
K1_q_a[1]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
K1_q_a[1]_PORT_A_address_reg = DFFE(K1_q_a[1]_PORT_A_address, K1_q_a[1]_clock_0, , , );
K1_q_a[1]_clock_0 = GLOBAL(PB1__clk0);
K1_q_a[1]_PORT_A_data_out = MEMORY(, , K1_q_a[1]_PORT_A_address_reg, , , , , , K1_q_a[1]_clock_0, , , , , );
L1_q_a[3] = K1_q_a[1]_PORT_A_data_out[1];


--A1L83 is ddsout_rom~773 at LC_X15_Y6_N2
--operation mode is normal

A1L83 = A1L68 & (A1L82 & (K1_q_a[1]) # !A1L82 & L1_q_a[1]) # !A1L68 & (A1L82);


--B1L186 is ddsc:i_dds|add~1291 at LC_X15_Y6_N8
--operation mode is arithmetic

B1L186 = M1_q_a[3] $ J1_q_a[3] $ B1L184;

--B1L187 is ddsc:i_dds|add~1293 at LC_X15_Y6_N8
--operation mode is arithmetic

B1L187_cout_0 = M1_q_a[3] & !J1_q_a[3] & !B1L184 # !M1_q_a[3] & (!B1L184 # !J1_q_a[3]);
B1L187 = CARRY(B1L187_cout_0);

--B1L188 is ddsc:i_dds|add~1293COUT1_1352 at LC_X15_Y6_N8
--operation mode is arithmetic

B1L188_cout_1 = M1_q_a[3] & !J1_q_a[3] & !B1L185 # !M1_q_a[3] & (!B1L185 # !J1_q_a[3]);
B1L188 = CARRY(B1L188_cout_1);


--L1_q_a[2] is ddsc:i_dds|lpm_rom:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated|q_a[2] at M4K_X13_Y9
--RAM Block Operation Mode: ROM
--Port A