dds_sin.fit.eqn

用vhdl编写的程序

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- (including device programming or simulation files), and any 
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--ddsout_rom[0] is ddsout_rom[0] at LC_X18_Y6_N9
--operation mode is normal

ddsout_rom[0]_lut_out = A1L80 # A1L77 # A1L81 & FB1L10;
ddsout_rom[0] = DFFEAS(ddsout_rom[0]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[1] is ddsout_rom[1] at LC_X15_Y6_N0
--operation mode is normal

ddsout_rom[1]_lut_out = A1L67 & (NB5L8) # !A1L67 & (A1L83);
ddsout_rom[1] = DFFEAS(ddsout_rom[1]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[2] is ddsout_rom[2] at LC_X19_Y6_N8
--operation mode is normal

ddsout_rom[2]_lut_out = A1L67 & (NB4L7 # !NB5L7) # !A1L67 & (A1L85);
ddsout_rom[2] = DFFEAS(ddsout_rom[2]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[3] is ddsout_rom[3] at LC_X15_Y3_N8
--operation mode is normal

ddsout_rom[3]_lut_out = A1L67 & (NB3L8) # !A1L67 & (A1L87);
ddsout_rom[3] = DFFEAS(ddsout_rom[3]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[4] is ddsout_rom[4] at LC_X15_Y4_N4
--operation mode is normal

ddsout_rom[4]_lut_out = A1L67 & NB2L8 # !A1L67 & (A1L89);
ddsout_rom[4] = DFFEAS(ddsout_rom[4]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[5] is ddsout_rom[5] at LC_X16_Y6_N2
--operation mode is normal

ddsout_rom[5]_lut_out = A1L67 & NB1L9 # !A1L67 & (A1L91);
ddsout_rom[5] = DFFEAS(ddsout_rom[5]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[6] is ddsout_rom[6] at LC_X16_Y5_N4
--operation mode is normal

ddsout_rom[6]_lut_out = A1L67 & (NB10L7 # !NB1L7) # !A1L67 & (A1L93);
ddsout_rom[6] = DFFEAS(ddsout_rom[6]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[7] is ddsout_rom[7] at LC_X15_Y3_N3
--operation mode is normal

ddsout_rom[7]_lut_out = A1L67 & (NB9L8) # !A1L67 & (A1L95);
ddsout_rom[7] = DFFEAS(ddsout_rom[7]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[8] is ddsout_rom[8] at LC_X11_Y3_N7
--operation mode is normal

ddsout_rom[8]_lut_out = A1L67 & NB8L8 # !A1L67 & (A1L97);
ddsout_rom[8] = DFFEAS(ddsout_rom[8]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--ddsout_rom[9] is ddsout_rom[9] at LC_X15_Y4_N8
--operation mode is normal

ddsout_rom[9]_lut_out = A1L67 & FB1L2 # !A1L67 & (A1L99);
ddsout_rom[9] = DFFEAS(ddsout_rom[9]_lut_out, !GLOBAL(sysclk), VCC, , , , , , );


--QB1_q_b[0] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[0] at M4K_X13_Y3
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[0]_PORT_A_data_in = BUS(DIN[0], DIN[3], DIN[6], DIN[7]);
QB1_q_b[0]_PORT_A_data_in_reg = DFFE(QB1_q_b[0]_PORT_A_data_in, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[0]_PORT_A_address_reg = DFFE(QB1_q_b[0]_PORT_A_address, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[0]_PORT_B_address_reg = DFFE(QB1_q_b[0]_PORT_B_address, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_PORT_A_write_enable = VCC;
QB1_q_b[0]_PORT_A_write_enable_reg = DFFE(QB1_q_b[0]_PORT_A_write_enable, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_read_enable = VCC;
QB1_q_b[0]_PORT_B_read_enable_reg = DFFE(QB1_q_b[0]_PORT_B_read_enable, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_clock_0 = GLOBAL(sysclk);
QB1_q_b[0]_clock_1 = GLOBAL(sysclk);
QB1_q_b[0]_PORT_B_data_out = MEMORY(QB1_q_b[0]_PORT_A_data_in_reg, , QB1_q_b[0]_PORT_A_address_reg, QB1_q_b[0]_PORT_B_address_reg, QB1_q_b[0]_PORT_A_write_enable_reg, QB1_q_b[0]_PORT_B_read_enable_reg, , , QB1_q_b[0]_clock_0, QB1_q_b[0]_clock_1, , , , );
QB1_q_b[0]_PORT_B_data_out_reg = DFFE(QB1_q_b[0]_PORT_B_data_out, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0] = QB1_q_b[0]_PORT_B_data_out_reg[0];

--QB1_q_b[7] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[7] at M4K_X13_Y3
QB1_q_b[0]_PORT_A_data_in = BUS(DIN[0], DIN[3], DIN[6], DIN[7]);
QB1_q_b[0]_PORT_A_data_in_reg = DFFE(QB1_q_b[0]_PORT_A_data_in, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[0]_PORT_A_address_reg = DFFE(QB1_q_b[0]_PORT_A_address, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[0]_PORT_B_address_reg = DFFE(QB1_q_b[0]_PORT_B_address, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_PORT_A_write_enable = VCC;
QB1_q_b[0]_PORT_A_write_enable_reg = DFFE(QB1_q_b[0]_PORT_A_write_enable, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_read_enable = VCC;
QB1_q_b[0]_PORT_B_read_enable_reg = DFFE(QB1_q_b[0]_PORT_B_read_enable, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_clock_0 = GLOBAL(sysclk);
QB1_q_b[0]_clock_1 = GLOBAL(sysclk);
QB1_q_b[0]_PORT_B_data_out = MEMORY(QB1_q_b[0]_PORT_A_data_in_reg, , QB1_q_b[0]_PORT_A_address_reg, QB1_q_b[0]_PORT_B_address_reg, QB1_q_b[0]_PORT_A_write_enable_reg, QB1_q_b[0]_PORT_B_read_enable_reg, , , QB1_q_b[0]_clock_0, QB1_q_b[0]_clock_1, , , , );
QB1_q_b[0]_PORT_B_data_out_reg = DFFE(QB1_q_b[0]_PORT_B_data_out, QB1_q_b[0]_clock_1, , , );
QB1_q_b[7] = QB1_q_b[0]_PORT_B_data_out_reg[3];

--QB1_q_b[6] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[6] at M4K_X13_Y3
QB1_q_b[0]_PORT_A_data_in = BUS(DIN[0], DIN[3], DIN[6], DIN[7]);
QB1_q_b[0]_PORT_A_data_in_reg = DFFE(QB1_q_b[0]_PORT_A_data_in, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[0]_PORT_A_address_reg = DFFE(QB1_q_b[0]_PORT_A_address, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[0]_PORT_B_address_reg = DFFE(QB1_q_b[0]_PORT_B_address, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_PORT_A_write_enable = VCC;
QB1_q_b[0]_PORT_A_write_enable_reg = DFFE(QB1_q_b[0]_PORT_A_write_enable, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_read_enable = VCC;
QB1_q_b[0]_PORT_B_read_enable_reg = DFFE(QB1_q_b[0]_PORT_B_read_enable, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_clock_0 = GLOBAL(sysclk);
QB1_q_b[0]_clock_1 = GLOBAL(sysclk);
QB1_q_b[0]_PORT_B_data_out = MEMORY(QB1_q_b[0]_PORT_A_data_in_reg, , QB1_q_b[0]_PORT_A_address_reg, QB1_q_b[0]_PORT_B_address_reg, QB1_q_b[0]_PORT_A_write_enable_reg, QB1_q_b[0]_PORT_B_read_enable_reg, , , QB1_q_b[0]_clock_0, QB1_q_b[0]_clock_1, , , , );
QB1_q_b[0]_PORT_B_data_out_reg = DFFE(QB1_q_b[0]_PORT_B_data_out, QB1_q_b[0]_clock_1, , , );
QB1_q_b[6] = QB1_q_b[0]_PORT_B_data_out_reg[2];

--QB1_q_b[3] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[3] at M4K_X13_Y3
QB1_q_b[0]_PORT_A_data_in = BUS(DIN[0], DIN[3], DIN[6], DIN[7]);
QB1_q_b[0]_PORT_A_data_in_reg = DFFE(QB1_q_b[0]_PORT_A_data_in, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[0]_PORT_A_address_reg = DFFE(QB1_q_b[0]_PORT_A_address, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[0]_PORT_B_address_reg = DFFE(QB1_q_b[0]_PORT_B_address, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_PORT_A_write_enable = VCC;
QB1_q_b[0]_PORT_A_write_enable_reg = DFFE(QB1_q_b[0]_PORT_A_write_enable, QB1_q_b[0]_clock_0, , , );
QB1_q_b[0]_PORT_B_read_enable = VCC;
QB1_q_b[0]_PORT_B_read_enable_reg = DFFE(QB1_q_b[0]_PORT_B_read_enable, QB1_q_b[0]_clock_1, , , );
QB1_q_b[0]_clock_0 = GLOBAL(sysclk);
QB1_q_b[0]_clock_1 = GLOBAL(sysclk);
QB1_q_b[0]_PORT_B_data_out = MEMORY(QB1_q_b[0]_PORT_A_data_in_reg, , QB1_q_b[0]_PORT_A_address_reg, QB1_q_b[0]_PORT_B_address_reg, QB1_q_b[0]_PORT_A_write_enable_reg, QB1_q_b[0]_PORT_B_read_enable_reg, , , QB1_q_b[0]_clock_0, QB1_q_b[0]_clock_1, , , , );
QB1_q_b[0]_PORT_B_data_out_reg = DFFE(QB1_q_b[0]_PORT_B_data_out, QB1_q_b[0]_clock_1, , , );
QB1_q_b[3] = QB1_q_b[0]_PORT_B_data_out_reg[1];


--QB1_q_b[1] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[1] at M4K_X13_Y2
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 2, Port B Depth: 1024, Port B Width: 2
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[1]_PORT_A_data_in = BUS(DIN[1], DIN[5]);
QB1_q_b[1]_PORT_A_data_in_reg = DFFE(QB1_q_b[1]_PORT_A_data_in, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[1]_PORT_A_address_reg = DFFE(QB1_q_b[1]_PORT_A_address, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[1]_PORT_B_address_reg = DFFE(QB1_q_b[1]_PORT_B_address, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1]_PORT_A_write_enable = VCC;
QB1_q_b[1]_PORT_A_write_enable_reg = DFFE(QB1_q_b[1]_PORT_A_write_enable, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_B_read_enable = VCC;
QB1_q_b[1]_PORT_B_read_enable_reg = DFFE(QB1_q_b[1]_PORT_B_read_enable, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1]_clock_0 = GLOBAL(sysclk);
QB1_q_b[1]_clock_1 = GLOBAL(sysclk);
QB1_q_b[1]_PORT_B_data_out = MEMORY(QB1_q_b[1]_PORT_A_data_in_reg, , QB1_q_b[1]_PORT_A_address_reg, QB1_q_b[1]_PORT_B_address_reg, QB1_q_b[1]_PORT_A_write_enable_reg, QB1_q_b[1]_PORT_B_read_enable_reg, , , QB1_q_b[1]_clock_0, QB1_q_b[1]_clock_1, , , , );
QB1_q_b[1]_PORT_B_data_out_reg = DFFE(QB1_q_b[1]_PORT_B_data_out, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1] = QB1_q_b[1]_PORT_B_data_out_reg[0];

--QB1_q_b[5] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[5] at M4K_X13_Y2
QB1_q_b[1]_PORT_A_data_in = BUS(DIN[1], DIN[5]);
QB1_q_b[1]_PORT_A_data_in_reg = DFFE(QB1_q_b[1]_PORT_A_data_in, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[1]_PORT_A_address_reg = DFFE(QB1_q_b[1]_PORT_A_address, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[1]_PORT_B_address_reg = DFFE(QB1_q_b[1]_PORT_B_address, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1]_PORT_A_write_enable = VCC;
QB1_q_b[1]_PORT_A_write_enable_reg = DFFE(QB1_q_b[1]_PORT_A_write_enable, QB1_q_b[1]_clock_0, , , );
QB1_q_b[1]_PORT_B_read_enable = VCC;
QB1_q_b[1]_PORT_B_read_enable_reg = DFFE(QB1_q_b[1]_PORT_B_read_enable, QB1_q_b[1]_clock_1, , , );
QB1_q_b[1]_clock_0 = GLOBAL(sysclk);
QB1_q_b[1]_clock_1 = GLOBAL(sysclk);
QB1_q_b[1]_PORT_B_data_out = MEMORY(QB1_q_b[1]_PORT_A_data_in_reg, , QB1_q_b[1]_PORT_A_address_reg, QB1_q_b[1]_PORT_B_address_reg, QB1_q_b[1]_PORT_A_write_enable_reg, QB1_q_b[1]_PORT_B_read_enable_reg, , , QB1_q_b[1]_clock_0, QB1_q_b[1]_clock_1, , , , );
QB1_q_b[1]_PORT_B_data_out_reg = DFFE(QB1_q_b[1]_PORT_B_data_out, QB1_q_b[1]_clock_1, , , );
QB1_q_b[5] = QB1_q_b[1]_PORT_B_data_out_reg[1];


--QB1_q_b[2] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[2] at M4K_X13_Y4
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
QB1_q_b[2]_PORT_A_data_in = BUS(DIN[2], DIN[4], DIN[8], DIN[9]);
QB1_q_b[2]_PORT_A_data_in_reg = DFFE(QB1_q_b[2]_PORT_A_data_in, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[2]_PORT_A_address_reg = DFFE(QB1_q_b[2]_PORT_A_address, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[2]_PORT_B_address_reg = DFFE(QB1_q_b[2]_PORT_B_address, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_PORT_A_write_enable = VCC;
QB1_q_b[2]_PORT_A_write_enable_reg = DFFE(QB1_q_b[2]_PORT_A_write_enable, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_read_enable = VCC;
QB1_q_b[2]_PORT_B_read_enable_reg = DFFE(QB1_q_b[2]_PORT_B_read_enable, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_clock_0 = GLOBAL(sysclk);
QB1_q_b[2]_clock_1 = GLOBAL(sysclk);
QB1_q_b[2]_PORT_B_data_out = MEMORY(QB1_q_b[2]_PORT_A_data_in_reg, , QB1_q_b[2]_PORT_A_address_reg, QB1_q_b[2]_PORT_B_address_reg, QB1_q_b[2]_PORT_A_write_enable_reg, QB1_q_b[2]_PORT_B_read_enable_reg, , , QB1_q_b[2]_clock_0, QB1_q_b[2]_clock_1, , , , );
QB1_q_b[2]_PORT_B_data_out_reg = DFFE(QB1_q_b[2]_PORT_B_data_out, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2] = QB1_q_b[2]_PORT_B_data_out_reg[0];

--QB1_q_b[9] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[9] at M4K_X13_Y4
QB1_q_b[2]_PORT_A_data_in = BUS(DIN[2], DIN[4], DIN[8], DIN[9]);
QB1_q_b[2]_PORT_A_data_in_reg = DFFE(QB1_q_b[2]_PORT_A_data_in, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[2]_PORT_A_address_reg = DFFE(QB1_q_b[2]_PORT_A_address, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[2]_PORT_B_address_reg = DFFE(QB1_q_b[2]_PORT_B_address, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_PORT_A_write_enable = VCC;
QB1_q_b[2]_PORT_A_write_enable_reg = DFFE(QB1_q_b[2]_PORT_A_write_enable, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_read_enable = VCC;
QB1_q_b[2]_PORT_B_read_enable_reg = DFFE(QB1_q_b[2]_PORT_B_read_enable, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_clock_0 = GLOBAL(sysclk);
QB1_q_b[2]_clock_1 = GLOBAL(sysclk);
QB1_q_b[2]_PORT_B_data_out = MEMORY(QB1_q_b[2]_PORT_A_data_in_reg, , QB1_q_b[2]_PORT_A_address_reg, QB1_q_b[2]_PORT_B_address_reg, QB1_q_b[2]_PORT_A_write_enable_reg, QB1_q_b[2]_PORT_B_read_enable_reg, , , QB1_q_b[2]_clock_0, QB1_q_b[2]_clock_1, , , , );
QB1_q_b[2]_PORT_B_data_out_reg = DFFE(QB1_q_b[2]_PORT_B_data_out, QB1_q_b[2]_clock_1, , , );
QB1_q_b[9] = QB1_q_b[2]_PORT_B_data_out_reg[3];

--QB1_q_b[8] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[8] at M4K_X13_Y4
QB1_q_b[2]_PORT_A_data_in = BUS(DIN[2], DIN[4], DIN[8], DIN[9]);
QB1_q_b[2]_PORT_A_data_in_reg = DFFE(QB1_q_b[2]_PORT_A_data_in, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_A_address = BUS(QWR[0], QWR[1], QWR[2], QWR[3], QWR[4], QWR[5], QWR[6], QWR[7], QWR[8], QWR[9]);
QB1_q_b[2]_PORT_A_address_reg = DFFE(QB1_q_b[2]_PORT_A_address, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_address = BUS(QRD[0], QRD[1], QRD[2], QRD[3], QRD[4], QRD[5], QRD[6], QRD[7], QRD[8], QRD[9]);
QB1_q_b[2]_PORT_B_address_reg = DFFE(QB1_q_b[2]_PORT_B_address, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_PORT_A_write_enable = VCC;
QB1_q_b[2]_PORT_A_write_enable_reg = DFFE(QB1_q_b[2]_PORT_A_write_enable, QB1_q_b[2]_clock_0, , , );
QB1_q_b[2]_PORT_B_read_enable = VCC;
QB1_q_b[2]_PORT_B_read_enable_reg = DFFE(QB1_q_b[2]_PORT_B_read_enable, QB1_q_b[2]_clock_1, , , );
QB1_q_b[2]_clock_0 = GLOBAL(sysclk);
QB1_q_b[2]_clock_1 = GLOBAL(sysclk);
QB1_q_b[2]_PORT_B_data_out = MEMORY(QB1_q_b[2]_PORT_A_data_in_reg, , QB1_q_b[2]_PORT_A_address_reg, QB1_q_b[2]_PORT_B_address_reg, QB1_q_b[2]_PORT_A_write_enable_reg, QB1_q_b[2]_PORT_B_read_enable_reg, , , QB1_q_b[2]_clock_0, QB1_q_b[2]_clock_1, , , , );
QB1_q_b[2]_PORT_B_data_out_reg = DFFE(QB1_q_b[2]_PORT_B_data_out, QB1_q_b[2]_clock_1, , , );
QB1_q_b[8] = QB1_q_b[2]_PORT_B_data_out_reg[2];

--QB1_q_b[4] is myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated|q_b[4] at M4K_X13_Y4