mul_6.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mul_6 is 
   port(clock: IN STD_LOGIC  := '1';	
      
		dataa_0		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		dataa_1		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		dataa_2		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		datab_0		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		datab_1		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		datab_2		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

        );
end;

architecture behave of mul_6 is
    

signal numer1: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal denom1: STD_LOGIC_VECTOR (5 DOWNTO 0):="010000";
  

component kk IS
	PORT
	(
		clock0		: IN STD_LOGIC  := '1';
		dataa_0		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		dataa_1		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		dataa_2		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		datab_0		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		datab_1		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		datab_2		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END component;


component ll IS-------------除法
	PORT
	(
		denom		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		numer		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		remain		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
END component;


signal aaa: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal bbb: STD_LOGIC_VECTOR (5 DOWNTO 0):="010000";
signal remain1 :STD_LOGIC_VECTOR (5 DOWNTO 0);    
begin 
u1:kk port map(clock0=>clock,dataa_0=>dataa_0,dataa_1=>dataa_1,dataa_2=>dataa_2,
          	datab_0=>datab_0,datab_1=>datab_1,datab_2=>datab_2,result=>aaa);

u2:ll port map(	denom=>bbb,numer=>aaa,quotient=>result,remain=>remain1);
end behave;