dds_sin.vhd

用vhdl编写的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dds_sin is
	port( sysclk : in std_logic; --系统时钟
	      RD : in std_logic;----波形存储使能
	      dclk:out std_logic; --------D/A时钟
	      
		  ddsout : out std_logic_vector(9 downto 0); --波形输出
		  ddsout2 : out std_logic_vector(9 downto 0);---存储输出
		  
		   sel : in std_logic_vector(1 downto 0); --高低字节频率输入选择
		  
                  fpin : in std_logic_vector(7 downto 0);频字输入
		  sselect:in std_logic_vector(1 downto 0);---波形选择
		  cmp_sel:in std_logic;------线性组合还是谐波组合
		  aa,bb,cc:in std_logic;-----线性组合系数

		  amp:in std_logic;--------幅度调节
		  amp_out:out std_logic_vector(7 downto 0)
		  );
end dds_sin;

architecture behave of dds_sin is

component myram IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END component;

component ppl2_5 IS
	PORT
	(
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC 
	);
END component;

component ddsc is
   		generic( freq_width : integer :=32;   --input freq width
			phase_width : integer :=16;  --input phase width
			adder_width : integer :=32;	 --adder width
			romad_width : integer :=10;  --address width
			romdat_width : integer :=10); --data width
   		port(clk : in std_logic;
			freqin : in std_logic_vector(freq_width-1 downto 0);
			phasein : in std_logic_vector(phase_width-1 downto 0);
			ddsout : out std_logic_vector(romdat_width-1 downto 0);
			SEL:in std_logic_vector(1 downto 0);
			aa,bb,cc:in std_logic;
			aacnt,bbcnt,cccnt:out std_logic_vector(3 downto 0);
		    ddsout11,ddsout22,ddsout33:out std_logic_vector(romdat_width-1 downto 0);
		   ddsout145:out std_logic_vector(romdat_width-1 downto 0);
		  romaddr_back:out std_logic_vector(9 downto 0)
		    );
		
end component ddsc;
	
component mul_6 IS       -----------乘法器
          port(clock: IN STD_LOGIC  := '1';	
      
		dataa_0		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		dataa_1		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		dataa_2		: IN STD_LOGIC_VECTOR (3 DOWNTO 0) :=  (OTHERS => '0');
		datab_0		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		datab_1		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		datab_2		: IN STD_LOGIC_VECTOR (9 DOWNTO 0) :=  (OTHERS => '0');
		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

        );
END component;

	signal selok:std_logic;
	signal pfsel : std_logic;
	signal clk : std_logic;
	signal freqind : std_logic_vector(31 downto 0);
	signal phaseind : std_logic_vector(15 downto 0);
	signal sysclk1:std_logic;
	signal tmp:std_logic_vector(9 downto 0);
	signal aa1,bb1,cc1:std_logic;
	signal aacnt1,bbcnt1,cccnt1:std_logic_vector(3 downto 0);
	signal ddsout111,ddsout222,ddsout333:std_logic_vector(9 downto 0);
	------
	signal ddsout_tmp:std_logic_vector(9 downto 0);
	signal ddsout_cmp:std_logic_vector(9 downto 0);
	signal ddsout_cmp1:std_logic_vector(9 downto 0);
	signal ddsout_145:std_logic_vector(9 downto 0);
	signal cmp_select:std_logic;-----组合波选择
	------------------
	signal count:std_logic_vector(7 downto 0):="00000000";
	------------------
	SIGNAL  QWR    : STD_LOGIC_VECTOR (9 DOWNTO 0); --对双口RAM写地址计数器
    SIGNAL  Q2     : STD_LOGIC_VECTOR (9 DOWNTO 0); 
    SIGNAL  QRD    : STD_LOGIC_VECTOR (9 DOWNTO 0); --对双口RAM读地址计数器
    SIGNAL  NOTCLK : STD_LOGIC ;
    SIGNAL    COUT : STD_LOGIC ;
    SIGNAL     WEN : STD_LOGIC ;
    SIGNAL  DIN    : STD_LOGIC_VECTOR (9 DOWNTO 0);
    signal ddsout_rom:STD_LOGIC_VECTOR (9 DOWNTO 0);
    signal cclk:std_logic;
	signal romaddr_temp:STD_LOGIC_VECTOR (9 DOWNTO 0);
	signal  ccclk:std_logic;
	
begin
	ppl:ppl2_5 port map(inclk0=>sysclk,c0=>sysclk1);
	i_dds: ddsc port map(clk=>clk,ddsout=>ddsout_tmp,phasein=>phaseind,freqin=>freqind,
	                     SEL=>sselect,aa=>aa,bb=>bb,cc=>cc,
	                     aacnt=>aacnt1,bbcnt=>bbcnt1,cccnt=>cccnt1,
	                     ddsout11=>ddsout111,ddsout22=>ddsout222,
	                     ddsout33=>ddsout333,ddsout145=>ddsout_145,
	                     romaddr_back=>romaddr_temp);
	mul:mul_6 port map(clock=>sysclk,dataa_0=>aacnt1,dataa_1=>bbcnt1,
	                   dataa_2=>cccnt1,
	                    datab_0=>ddsout111,datab_1=>ddsout222,datab_2=>ddsout333,
	                    result(9 downto 0)=>ddsout_cmp1);
	ram: myram PORT MAP(data => DIN ,  wren => WEN, wraddress => QWR,rdaddress => QRD,
                         q => ddsout2, clock=>sysclk );	
	------------------
	clk<=sysclk1;
	dclk<=sysclk;
	selok<='1';
	pfsel<='1';
	ccclk<=romaddr_temp(0);
	cmp_select<=not(sselect(1) and sselect(0));
	
	process(sysclk1)
	begin
           
		if rising_edge(sysclk1) then
			if(selok='1' and pfsel = '1') then
				if(sel="00") then
				freqind(7 downto 0)<=fpin;
				elsif sel="01" then
					freqind(15 downto 8)<=fpin;
				elsif sel="10" then
					freqind(23 downto 16)<=fpin;
				else 	
				    freqind(31 downto 24)<=fpin;
				end if;
			elsif(selok='1' and pfsel = '0') then
				phaseind(7 downto 0)<=fpin;
			end if;
		end if;
		
	end process;
	
	


   process(romaddr_temp,RD)
     begin
         if rising_edge(ccclk) then
       if RD='0' then
                 QRD<="0000000000";WEN <=not RD;DIN <= ddsout_rom; QWR<=QWR+1;
       else 
              QRD<=QRD+1; QWR<="0000000000";
            
       end if;
      if QRD="1111111111" then 
           QRD<="0000000000";
      end if;
     -- if QWR="1111111111" then 
         -- QWR<="0000000000";
     --end if;
       end if;
    end process;




	----------------------------------
	process(sysclk)
	begin
	     
	     if  cmp_sel='1' then
	          ddsout_cmp<=ddsout_cmp1 ;
	     else 
	        ddsout_cmp<= ddsout_145;
	     end if;
	end process;
	
	process(notclk)
	begin
	   if rising_edge(notclk) then
	     if cmp_select='1' then  
	            ddsout_rom<=ddsout_tmp;
	     else 
	         ddsout_rom<= ddsout_cmp ;
          end if;
       end if;
   end process;
	-----------------
    process(amp)
	  begin
	      if rising_edge(amp) then
	          count<=count+5;
	       end if;
	  end process;
	
	-------
	ddsout <= ddsout_rom;
	amp_out<= count;
	
	-----
	
end behave;