ddsc.vhd

用vhdl编写的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;
entity ddsc is 
   generic( freq_width : integer :=32;   --input freq width
			phase_width : integer :=16;  --input phase width
			adder_width : integer :=32;	 --adder width
			romad_width : integer :=10;  --address width
			romdat_width : integer :=10); --data width
   port(clk : in std_logic;
		freqin : in std_logic_vector(freq_width-1 downto 0);
		phasein : in std_logic_vector(phase_width-1 downto 0);
		ddsout : out std_logic_vector(romdat_width-1 downto 0);
		ddsout145:out std_logic_vector(romdat_width-1 downto 0);
		SEL:in std_logic_vector(1 downto 0);
		aa,bb,cc:in std_logic;
		aacnt,bbcnt,cccnt:out std_logic_vector(3 downto 0);
		ddsout11,ddsout22,ddsout33:out std_logic_vector(romdat_width-1 downto 0);
		romaddr_back:out std_logic_vector(9 downto 0));
end entity ddsc;
architecture behave of ddsc is
	signal acc : std_logic_vector(adder_width-1 downto 0);
	---3
	signal acc1 : std_logic_vector(adder_width-1 downto 0);
	signal acc2 : std_logic_vector(adder_width-1 downto 0);
	signal ss_tmp:std_logic_vector(romdat_width downto 0);
	---3
	signal phaseadd : std_logic_vector(phase_width-1 downto 0);
	signal phaseadd1 : std_logic_vector(phase_width-1 downto 0);
	signal phaseadd2 : std_logic_vector(phase_width-1 downto 0);
	signal romaddr : std_logic_vector(romad_width-1 downto 0);
	signal romaddr1 : std_logic_vector(romad_width-1 downto 0);
	signal romaddr2 : std_logic_vector(romad_width-1 downto 0);
	signal freqw : std_logic_vector(freq_width-1 downto 0);
	signal freqw1 : std_logic_vector(freq_width-1 downto 0);
	signal freqw2 : std_logic_vector(freq_width-1 downto 0);
	signal phasew : std_logic_vector(phase_width-1 downto 0);
	signal phasew1 : std_logic_vector(phase_width-1 downto 0);
	signal phasew2 : std_logic_vector(phase_width-1 downto 0);
	signal ddsout1:std_logic_vector(romdat_width-1 downto 0);
	signal ddsout2:std_logic_vector(romdat_width-1 downto 0);
	signal ddsout3:std_logic_vector(romdat_width-1 downto 0);
	signal ddsout4:std_logic_vector(romdat_width-1 downto 0);
	signal ddsout5:std_logic_vector(romdat_width-1 downto 0);
	--------------------------------
	signal aacnt1,bbcnt1,cccnt1:std_logic_vector(3 downto 0);
	
	------
	signal tmp1:std_logic_vector(freq_width+2 downto 0);
	signal tmp2:std_logic_vector(freq_width+2 downto 0);
	signal tmp3:std_logic_vector(freq_width+2 downto 0);
	
	
	
	
begin
    process(aa)
    begin
        if rising_edge(aa) then
            if aacnt1=9 then 
                aacnt1<="0000";
            else 
                aacnt1<=aacnt1+1;
            end if;
        end if;
         
    end process;
    process(bb)
    begin
        if rising_edge(bb) then
            if bbcnt1=9 then 
                bbcnt1<="0000";
            else 
                bbcnt1<=bbcnt1+1;
            end if;
        end if;

    end process;
    process(cc)
    begin
        if rising_edge(cc) then
            if cccnt1=9 then 
                cccnt1<="0000";
            else 
                cccnt1<=cccnt1+1;
            end if;
        end if;
     
    end process;
	
	process(clk)
	begin
		if rising_edge(clk) then
			freqw<= freqin;
			
			phasew <= phasein;
			acc <= acc + freqw;
		end if;
	end process;
	-------------------------
	
	
	process(clk)
	begin
	    if rising_edge(clk) then
			freqw1<= freqin;
			phasew1 <= phasein;
			tmp1(freq_width+2 downto freq_width+1)<="00";
			tmp1(freq_width downto 1)<=freqw1;
            tmp1(0)<='0';
            acc1 <= acc1 + tmp1(freq_width-1 downto 0);
			
		end if;
	end process; 
	
	process(clk)
	begin
	    if rising_edge(clk) then
			freqw2<= freqin;
			phasew2 <= phasein;
			tmp2(freq_width+2 )<='0';
			tmp2(freq_width+1 downto 2)<=freqw2;
            tmp2(1 downto 0)<="00";
            acc2 <= acc2 + tmp2(freq_width-1 downto 0);
			
		end if;
	end process;
	-----------------
	
	
	phaseadd <= acc(adder_width-1 downto adder_width-phase_width) + phasew;
	romaddr<= phaseadd(phase_width-1 downto phase_width-romad_width);
	----3
	phaseadd1 <= acc1(adder_width-1 downto adder_width-phase_width) + phasew1;
	romaddr1<= phaseadd1(phase_width-1 downto phase_width-romad_width);
	phaseadd2 <= acc2(adder_width-1 downto adder_width-phase_width) + phasew2;
	romaddr2<= phaseadd2(phase_width-1 downto phase_width-romad_width);
	--------3
	i_rom1: lpm_rom generic map(LPM_WIDTH => romdat_width,LPM_WIDTHAD => romad_width,
		LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA=>"REGISTERED",
		LPM_FILE=>"sinbo.mif")
		port map(outclock => clk, address => romaddr, q=> ddsout1) ;
	i_rom2: lpm_rom generic map(LPM_WIDTH => romdat_width,LPM_WIDTHAD => romad_width,
		LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA=>"REGISTERED",
		LPM_FILE=>"fangbo.mif")
		port map(outclock => clk, address => romaddr, q=> ddsout2)  ;
	i_rom3: lpm_rom generic map(LPM_WIDTH => romdat_width,LPM_WIDTHAD => romad_width,
		LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA=>"REGISTERED",
		LPM_FILE=>"sanjiao.mif")
		port map(outclock => clk, address => romaddr, q=> ddsout3);
		
    --------3
    i_rom4:lpm_rom generic map(LPM_WIDTH => romdat_width,LPM_WIDTHAD => romad_width,
		LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA=>"REGISTERED",
		LPM_FILE=>"sinbo1.mif")
		port map(outclock => clk, address => romaddr1, q=> ddsout4) ;
    --i_rom5:lpm_rom generic map(LPM_WIDTH => romdat_width,LPM_WIDTHAD => romad_width,
	--	LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA=>"REGISTERED",
		--LPM_FILE=>"sinbo2.mif")
		--port map(outclock => clk, address => romaddr2, q=> ddsout5) ;
    process(clk)
    begin
        ss_tmp<=('0'&ddsout1)+('0'&ddsout4);
        ddsout145<=ss_tmp(romdat_width downto 1);------------基波和二次谐波相加
    end process;
   ------3
		aacnt<=aacnt1;
		bbcnt<=bbcnt1;
		cccnt<=cccnt1;
		
		    ddsout<=ddsout1 when SEL="00" else
		            ddsout2 when SEL="01" else
		            ddsout3 when SEL="10" else
		            ddsout1;
		
	
      ddsout11<=ddsout1;
      ddsout22<=ddsout2;
      ddsout33<=ddsout3;
 
     romaddr_back<=romaddr;
end architecture behave;