zong.rpt

数字秒表的整个设计以及程序．波形仿真都在里面的了

         # !_LC059 & !_LC066 & !_LC078 & !_LC089 & !_LC093 &  _X014 &  _X015 & 
              _X016 &  _X017 &  _X018 &  _X019 &  _X020;
  _X014  = EXP( _LC066 & !_LC071 &  _LC074 & !_LC081);
  _X015  = EXP( _LC071 &  _LC074 & !_LC078);
  _X016  = EXP( _LC066 &  _LC071 & !_LC074 & !_LC084);
  _X017  = EXP(!_LC056 &  _LC066 & !_LC071 & !_LC074);
  _X018  = EXP(!_LC066 & !_LC071 &  _LC074 & !_LC089);
  _X019  = EXP(!_LC066 &  _LC071 & !_LC074 & !_LC093);
  _X020  = EXP(!_LC059 & !_LC066 & !_LC071 & !_LC074);

-- Node name is '|MULX:3|~492~1' 
-- Equation name is '_LC078', type is buried 
-- synthesized logic cell 
_LC078   = LCELL( _EQ081 $  _EQ082);
  _EQ081 = !_LC056 &  _LC066 & !_LC078 & !_LC081 & !_LC084 &  _X014 &  _X015 & 
              _X016 &  _X017 &  _X018 &  _X019 &  _X020
         # !_LC056 & !_LC059 & !_LC071 & !_LC081 & !_LC089 &  _X014 &  _X015 & 
              _X016 &  _X017 &  _X018 &  _X019 &  _X020
         # !_LC056 & !_LC059 & !_LC074 & !_LC084 & !_LC093 &  _X014 &  _X015 & 
              _X016 &  _X017 &  _X018 &  _X019 &  _X020
         #  _LC073;
  _X014  = EXP( _LC066 & !_LC071 &  _LC074 & !_LC081);
  _X015  = EXP( _LC071 &  _LC074 & !_LC078);
  _X016  = EXP( _LC066 &  _LC071 & !_LC074 & !_LC084);
  _X017  = EXP(!_LC056 &  _LC066 & !_LC071 & !_LC074);
  _X018  = EXP(!_LC066 & !_LC071 &  _LC074 & !_LC089);
  _X019  = EXP(!_LC066 &  _LC071 & !_LC074 & !_LC093);
  _X020  = EXP(!_LC059 & !_LC066 & !_LC071 & !_LC074);
  _EQ082 =  _X014 &  _X015 &  _X016 &  _X017 &  _X018 &  _X019 &  _X020;
  _X014  = EXP( _LC066 & !_LC071 &  _LC074 & !_LC081);
  _X015  = EXP( _LC071 &  _LC074 & !_LC078);
  _X016  = EXP( _LC066 &  _LC071 & !_LC074 & !_LC084);
  _X017  = EXP(!_LC056 &  _LC066 & !_LC071 & !_LC074);
  _X018  = EXP(!_LC066 & !_LC071 &  _LC074 & !_LC089);
  _X019  = EXP(!_LC066 &  _LC071 & !_LC074 & !_LC093);
  _X020  = EXP(!_LC059 & !_LC066 & !_LC071 & !_LC074);

-- Node name is '|MULX:3|~513~1~2' 
-- Equation name is '_LC060', type is buried 
-- synthesized logic cell 
_LC060   = LCELL( _EQ083 $  GND);
  _EQ083 = !_LC053 & !_LC057 & !_LC063 & !_LC082 & !_LC085 & !_LC092 & 
             !_LC096 &  _X021 &  _X022 &  _X023 &  _X024 &  _X025 &  _X026 & 
              _X027
         # !_LC053 & !_LC063 & !_LC066 & !_LC082 & !_LC092 &  _X021 &  _X022 & 
              _X023 &  _X024 &  _X025 &  _X026 &  _X027;
  _X021  = EXP( _LC066 & !_LC071 &  _LC074 & !_LC096);
  _X022  = EXP(!_LC063 &  _LC071 &  _LC074);
  _X023  = EXP( _LC066 &  _LC071 & !_LC074 & !_LC085);
  _X024  = EXP(!_LC057 &  _LC066 & !_LC071 & !_LC074);
  _X025  = EXP(!_LC066 & !_LC071 &  _LC074 & !_LC082);
  _X026  = EXP(!_LC066 &  _LC071 & !_LC074 & !_LC092);
  _X027  = EXP(!_LC053 & !_LC066 & !_LC071 & !_LC074);

-- Node name is '|MULX:3|~513~1' 
-- Equation name is '_LC063', type is buried 
-- synthesized logic cell 
_LC063   = LCELL( _EQ084 $  _EQ085);
  _EQ084 = !_LC057 & !_LC063 &  _LC066 & !_LC085 & !_LC096 &  _X021 &  _X022 & 
              _X023 &  _X024 &  _X025 &  _X026 &  _X027
         # !_LC053 & !_LC057 & !_LC071 & !_LC082 & !_LC096 &  _X021 &  _X022 & 
              _X023 &  _X024 &  _X025 &  _X026 &  _X027
         # !_LC053 & !_LC057 & !_LC074 & !_LC085 & !_LC092 &  _X021 &  _X022 & 
              _X023 &  _X024 &  _X025 &  _X026 &  _X027
         #  _LC060;
  _X021  = EXP( _LC066 & !_LC071 &  _LC074 & !_LC096);
  _X022  = EXP(!_LC063 &  _LC071 &  _LC074);
  _X023  = EXP( _LC066 &  _LC071 & !_LC074 & !_LC085);
  _X024  = EXP(!_LC057 &  _LC066 & !_LC071 & !_LC074);
  _X025  = EXP(!_LC066 & !_LC071 &  _LC074 & !_LC082);
  _X026  = EXP(!_LC066 &  _LC071 & !_LC074 & !_LC092);
  _X027  = EXP(!_LC053 & !_LC066 & !_LC071 & !_LC074);
  _EQ085 =  _X021 &  _X022 &  _X023 &  _X024 &  _X025 &  _X026 &  _X027;
  _X021  = EXP( _LC066 & !_LC071 &  _LC074 & !_LC096);
  _X022  = EXP(!_LC063 &  _LC071 &  _LC074);
  _X023  = EXP( _LC066 &  _LC071 & !_LC074 & !_LC085);
  _X024  = EXP(!_LC057 &  _LC066 & !_LC071 & !_LC074);
  _X025  = EXP(!_LC066 & !_LC071 &  _LC074 & !_LC082);
  _X026  = EXP(!_LC066 &  _LC071 & !_LC074 & !_LC092);
  _X027  = EXP(!_LC053 & !_LC066 & !_LC071 & !_LC074);

-- Node name is '|MULX:3|~531~1' 
-- Equation name is '_LC034', type is buried 
-- synthesized logic cell 
_LC034   = LCELL( _EQ086 $  VCC);
  _EQ086 = !_LC047 & !_LC066 & !_LC071 & !_LC074
         # !_LC047 &  _LC071 &  _LC074
         #  _LC066 & !_LC071 &  _LC074;

-- Node name is '|MULX:3|~534~1' 
-- Equation name is '_LC047', type is buried 
-- synthesized logic cell 
_LC047   = LCELL( _EQ087 $  _LC034);
  _EQ087 = !_LC047 & !_LC066 & !_LC071 & !_LC074;

-- Node name is '|MULX:3|~552~1' 
-- Equation name is '_LC038', type is buried 
-- synthesized logic cell 
_LC038   = LCELL( _EQ088 $  VCC);
  _EQ088 = !_LC042 & !_LC066 & !_LC071 & !_LC074
         # !_LC042 &  _LC071 &  _LC074;

-- Node name is '|MULX:3|~555~1' 
-- Equation name is '_LC042', type is buried 
-- synthesized logic cell 
_LC042   = LCELL( _EQ089 $  _LC038);
  _EQ089 = !_LC042 & !_LC066 & !_LC071 & !_LC074;

-- Node name is '|MULX:3|~573~1' 
-- Equation name is '_LC043', type is buried 
-- synthesized logic cell 
_LC043   = LCELL( _EQ090 $  VCC);
  _EQ090 = !_LC045 & !_LC066 & !_LC071 & !_LC074
         # !_LC045 &  _LC071 &  _LC074
         #  _LC066 &  _LC071 & !_LC074;

-- Node name is '|MULX:3|~576~1' 
-- Equation name is '_LC045', type is buried 
-- synthesized logic cell 
_LC045   = LCELL( _EQ091 $  _LC043);
  _EQ091 = !_LC045 & !_LC066 & !_LC071 & !_LC074;

-- Node name is '|MULX:3|~594~1' 
-- Equation name is '_LC048', type is buried 
-- synthesized logic cell 
_LC048   = LCELL( _EQ092 $  VCC);
  _EQ092 = !_LC044 &  _LC071 &  _LC074
         # !_LC066 &  _LC071 & !_LC074
         # !_LC044 & !_LC066 & !_LC074;

-- Node name is '|MULX:3|~597~1' 
-- Equation name is '_LC044', type is buried 
-- synthesized logic cell 
_LC044   = LCELL( _EQ093 $  _LC048);
  _EQ093 = !_LC044 & !_LC066 & !_LC071 & !_LC074;

-- Node name is '|MULX:3|~615~1' 
-- Equation name is '_LC028', type is buried 
-- synthesized logic cell 
_LC028   = LCELL( _EQ094 $  VCC);
  _EQ094 = !_LC019 &  _LC071 &  _LC074
         #  _LC066 & !_LC071 & !_LC074
         # !_LC019 & !_LC071 & !_LC074;

-- Node name is '|MULX:3|~618~1' 
-- Equation name is '_LC019', type is buried 
-- synthesized logic cell 
_LC019   = LCELL( _EQ095 $  _LC028);
  _EQ095 = !_LC019 & !_LC066 & !_LC071 & !_LC074;

-- Node name is '|MULX:3|~636~1' 
-- Equation name is '_LC025', type is buried 
-- synthesized logic cell 
_LC025   = LCELL( _EQ096 $  VCC);
  _EQ096 = !_LC026 & !_LC066 & !_LC071 & !_LC074
         # !_LC026 &  _LC071 &  _LC074;

-- Node name is '|MULX:3|~639~1' 
-- Equation name is '_LC026', type is buried 
-- synthesized logic cell 
_LC026   = LCELL( _EQ097 $  _LC025);
  _EQ097 =  _LC025 & !_LC066 & !_LC071 & !_LC074;

-- Node name is '|SEG7:2|~331~1' 
-- Equation name is '_LC079', type is buried 
-- synthesized logic cell 
_LC079   = LCELL( _EQ098 $ !_LC070);
  _EQ098 = !_LC063 & !_LC070 & !_LC078 &  _LC083
         # !_LC078 & !_LC083;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    e:\18052034\d1\zong.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,641K