📄 zong.rpt
字号:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\18052034\d1\zong.rpt
zong
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 54 D SOFT t 0 0 0 0 3 0 1 |CNT10:4|LPM_ADD_SUB:77|addcore:adder|addcore:adder0|result_node2
(36) 49 D DFFE + t 1 0 0 0 4 1 29 |CNT10:4|:4
- 50 D DFFE + t 0 0 0 0 5 1 29 |CNT10:4|:6
(37) 51 D DFFE + t 0 0 0 0 3 1 30 |CNT10:4|:8
- 52 D DFFE + t 0 0 0 0 4 1 30 |CNT10:4|:10
- 95 F TFFE t 0 0 0 0 11 0 9 |jishu:1|CNT6:5|:4
(57) 84 F TFFE t 0 0 0 0 11 0 9 |jishu:1|CNT6:5|:6
- 85 F TFFE t 0 0 0 0 11 0 9 |jishu:1|CNT6:5|:8
- 87 F TFFE t 0 0 0 0 11 0 5 |jishu:1|CNT6:6|:4
(56) 81 F TFFE t 0 0 0 0 11 0 5 |jishu:1|CNT6:6|:6
(65) 96 F TFFE t 0 0 0 0 11 0 5 |jishu:1|CNT6:6|:8
- 62 D DFFE t 1 0 0 0 9 0 10 |jishu:1|CNT10:1|:4
(44) 61 D TFFE t 0 0 0 0 9 0 9 |jishu:1|CNT10:1|:6
(42) 59 D DFFE t 0 0 0 0 8 0 10 |jishu:1|CNT10:1|:8
(39) 53 D DFFE t 0 0 0 0 9 0 10 |jishu:1|CNT10:1|:10
(64) 94 F TFFE t 1 0 1 0 12 0 10 |jishu:1|CNT10:2|:4
(60) 88 F TFFE t 0 0 0 0 12 0 8 |jishu:1|CNT10:2|:6
- 93 F TFFE t 0 0 0 0 11 0 9 |jishu:1|CNT10:2|:8
(62) 92 F TFFE t 0 0 0 0 12 0 9 |jishu:1|CNT10:2|:10
- 90 F TFFE t 1 0 1 0 11 0 9 |jishu:1|CNT10:3|:4
- 91 F TFFE t 0 0 0 0 11 0 8 |jishu:1|CNT10:3|:6
(61) 89 F TFFE t 0 0 0 0 10 0 9 |jishu:1|CNT10:3|:8
- 82 F TFFE t 0 0 0 0 11 0 9 |jishu:1|CNT10:3|:10
- 55 D TFFE t 1 0 1 0 12 0 11 |jishu:1|CNT10:4|:4
- 58 D TFFE t 0 0 0 0 12 0 9 |jishu:1|CNT10:4|:6
(40) 56 D TFFE t 0 0 0 0 11 0 10 |jishu:1|CNT10:4|:8
(41) 57 D TFFE t 0 0 0 0 12 0 10 |jishu:1|CNT10:4|:10
- 36 C DFFE t 0 0 0 0 6 0 4 |KEY:7|:3
- 39 C TFFE t 0 0 0 1 5 0 1 |KEY:7|state1 (|KEY:7|:5)
(30) 37 C DFFE t 0 0 0 1 4 0 2 |KEY:7|state0 (|KEY:7|:6)
- 74 E DFFE + t 0 0 0 0 3 6 24 |MULX:3|:24
- 71 E DFFE + t 0 0 0 0 3 6 24 |MULX:3|:26
- 66 E TFFE + t 0 0 0 0 3 6 24 |MULX:3|:28
- 68 E LCELL s t 3 2 1 0 8 0 1 |MULX:3|~450~1~2
- 76 E LCELL s t 2 2 0 0 8 0 1 |MULX:3|~450~1~3
- 70 E LCELL s t 3 2 1 0 8 7 4 |MULX:3|~450~1
(59) 86 F LCELL s t 7 7 0 0 10 0 1 |MULX:3|~471~1~2
- 83 F LCELL s t 8 7 1 0 11 7 3 |MULX:3|~471~1
(51) 73 E LCELL s t 7 7 0 0 10 0 1 |MULX:3|~492~1~2
- 78 E LCELL s t 8 7 1 0 11 7 3 |MULX:3|~492~1
- 60 D LCELL s t 7 7 0 0 10 0 1 |MULX:3|~513~1~2
- 63 D LCELL s t 8 7 1 0 11 7 3 |MULX:3|~513~1
- 34 C SOFT s t 0 0 0 0 4 1 1 |MULX:3|~531~1
- 47 C LCELL s t 0 0 0 0 5 1 2 |MULX:3|~534~1
- 38 C SOFT s t 0 0 0 0 4 1 1 |MULX:3|~552~1
- 42 C LCELL s t 0 0 0 0 5 1 2 |MULX:3|~555~1
(27) 43 C SOFT s t 0 0 0 0 4 1 1 |MULX:3|~573~1
(25) 45 C LCELL s t 0 0 0 0 5 1 2 |MULX:3|~576~1
(24) 48 C SOFT s t 0 0 0 0 4 1 1 |MULX:3|~594~1
- 44 C LCELL s t 0 0 0 0 5 1 2 |MULX:3|~597~1
- 28 B SOFT s t 0 0 0 0 4 1 1 |MULX:3|~615~1
(22) 19 B LCELL s t 0 0 0 0 5 1 2 |MULX:3|~618~1
(18) 25 B SOFT s t 0 0 0 0 4 1 1 |MULX:3|~636~1
- 26 B LCELL s t 0 0 0 0 4 0 1 |MULX:3|~639~1
- 79 E SOFT s t 0 0 0 0 4 1 0 |SEG7:2|~331~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\18052034\d1\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------- LC28 |MULX:3|~615~1
| +--------- LC19 |MULX:3|~618~1
| | +------- LC25 |MULX:3|~636~1
| | | +----- LC26 |MULX:3|~639~1
| | | | +--- LC17 seg0
| | | | | +- LC21 seg1
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'B'
LC | | | | | | | A B C D E F | Logic cells that feed LAB 'B':
LC28 -> - * - - - * | - * - - - - | <-- |MULX:3|~615~1
LC19 -> * * - - - * | - * - - - - | <-- |MULX:3|~618~1
LC25 -> - - - * * - | - * - - - - | <-- |MULX:3|~636~1
LC26 -> - - * - - - | - * - - - - | <-- |MULX:3|~639~1
Pin
67 -> - - - - - - | - - - - - - | <-- clk
1 -> - - - - - - | - - - - - - | <-- clr
LC74 -> * * * * * * | - * * * * * | <-- |MULX:3|:24
LC71 -> * * * * * * | - * * * * * | <-- |MULX:3|:26
LC66 -> * * * * * * | - * * * * * | <-- |MULX:3|:28
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\18052034\d1\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC36 |KEY:7|:3
| +--------------------------- LC39 |KEY:7|state1
| | +------------------------- LC37 |KEY:7|state0
| | | +----------------------- LC34 |MULX:3|~531~1
| | | | +--------------------- LC47 |MULX:3|~534~1
| | | | | +------------------- LC38 |MULX:3|~552~1
| | | | | | +----------------- LC42 |MULX:3|~555~1
| | | | | | | +--------------- LC43 |MULX:3|~573~1
| | | | | | | | +------------- LC45 |MULX:3|~576~1
| | | | | | | | | +----------- LC48 |MULX:3|~594~1
| | | | | | | | | | +--------- LC44 |MULX:3|~597~1
| | | | | | | | | | | +------- LC33 seg2
| | | | | | | | | | | | +----- LC35 seg3
| | | | | | | | | | | | | +--- LC40 seg4
| | | | | | | | | | | | | | +- LC41 seg5
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'C':
LC39 -> * * - - - - - - - - - - - - - | - - * - - - | <-- |KEY:7|state1
LC37 -> * * - - - - - - - - - - - - - | - - * - - - | <-- |KEY:7|state0
LC34 -> - - - - * - - - - - - - - - * | - - * - - - | <-- |MULX:3|~531~1
LC47 -> - - - * * - - - - - - - - - * | - - * - - - | <-- |MULX:3|~534~1
LC38 -> - - - - - - * - - - - - - * - | - - * - - - | <-- |MULX:3|~552~1
LC42 -> - - - - - * * - - - - - - * - | - - * - - - | <-- |MULX:3|~555~1
LC43 -> - - - - - - - - * - - - * - - | - - * - - - | <-- |MULX:3|~573~1
LC45 -> - - - - - - - * * - - - * - - | - - * - - - | <-- |MULX:3|~576~1
LC48 -> - - - - - - - - - - * * - - - | - - * - - - | <-- |MULX:3|~594~1
LC44 -> - - - - - - - - - * * * - - - | - - * - - - | <-- |MULX:3|~597~1
Pin
67 -> - - - - - - - - - - - - - - - | - - - - - - | <-- clk
1 -> - - - - - - - - - - - - - - - | - - - - - - | <-- clr
13 -> - * * - - - - - - - - - - - - | - - * - - - | <-- s_p
LC49 -> * * * - - - - - - - - - - - - | - - * * - * | <-- |CNT10:4|:4
LC50 -> * * * - - - - - - - - - - - - | - - * * - * | <-- |CNT10:4|:6
LC51 -> * * * - - - - - - - - - - - - | - - * * - * | <-- |CNT10:4|:8
LC52 -> * * * - - - - - - - - - - - - | - - * * - * | <-- |CNT10:4|:10
LC74 -> - - - * * * * * * * * * * * * | - * * * * * | <-- |MULX:3|:24
LC71 -> - - - * * * * * * * * * * * * | - * * * * * | <-- |MULX:3|:26
LC66 -> - - - * * * * * * * * * * * * | - * * * * * | <-- |MULX:3|:28
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\18052034\d1\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC64 clk10ms
| +----------------------------- LC54 |CNT10:4|LPM_ADD_SUB:77|addcore:adder|addcore:adder0|result_node2
| | +--------------------------- LC49 |CNT10:4|:4
| | | +------------------------- LC50 |CNT10:4|:6
| | | | +----------------------- LC51 |CNT10:4|:8
| | | | | +--------------------- LC52 |CNT10:4|:10
| | | | | | +------------------- LC62 |jishu:1|CNT10:1|:4
| | | | | | | +----------------- LC61 |jishu:1|CNT10:1|:6
| | | | | | | | +--------------- LC59 |jishu:1|CNT10:1|:8
| | | | | | | | | +------------- LC53 |jishu:1|CNT10:1|:10
| | | | | | | | | | +----------- LC55 |jishu:1|CNT10:4|:4
| | | | | | | | | | | +--------- LC58 |jishu:1|CNT10:4|:6
| | | | | | | | | | | | +------- LC56 |jishu:1|CNT10:4|:8
| | | | | | | | | | | | | +----- LC57 |jishu:1|CNT10:4|:10
| | | | | | | | | | | | | | +--- LC60 |MULX:3|~513~1~2
| | | | | | | | | | | | | | | +- LC63 |MULX:3|~513~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'D':
LC54 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |CNT10:4|LPM_ADD_SUB:77|addcore:adder|addcore:adder0|result_node2
LC49 -> * - * * * * * * * * * * * * - - | - - * * - * | <-- |CNT10:4|:4
LC50 -> * * * * - * * * * * * * * * - - | - - * * - * | <-- |CNT10:4|:6
LC51 -> * * * * * * * * * * * * * * - - | - - * * - * | <-- |CNT10:4|:8
LC52 -> * * * * * * * * * * * * * * - - | - - * * - * | <-- |CNT10:4|:10
LC62 -> - - - - - - * * * * * * * * - - | - - - * * - | <-- |jishu:1|CNT10:1|:4
LC61 -> - - - - - - * * - * * * * * - - | - - - * - * | <-- |jishu:1|CNT10:1|:6
LC59 -> - - - - - - * * * * * * * * - - | - - - * * - | <-- |jishu:1|CNT10:1|:8
LC53 -> - - - - - - * * * * * * * * * * | - - - * - - | <-- |jishu:1|CNT10:1|:10
LC55 -> - - - - - - - - - - * * * * - - | - - - * * * | <-- |jishu:1|CNT10:4|:4
LC58 -> - - - - - - - - - - * * - * - - | - - - * - * | <-- |jishu:1|CNT10:4|:6
LC56 -> - - - - - - - - - - * * * * - - | - - - * * * | <-- |jishu:1|CNT10:4|:8
LC57 -> - - - - - - - - - - * * * * * * | - - - * - * | <-- |jishu:1|CNT10:4|:10
LC60 -> - - - - - - - - - - - - - - - * | - - - * - - | <-- |MULX:3|~513~1~2
LC63 -> - - - - - - - - - - - - - - * * | - - - * * - | <-- |MULX:3|~513~1
Pin
67 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
1 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clr
LC85 -> - - - - - - - - - - - - - - * * | - - - * - * | <-- |jishu:1|CNT6:5|:8
LC96 -> - - - - - - - - - - - - - - * * | - - - * - * | <-- |jishu:1|CNT6:6|:8
LC92 -> - - - - - - - - - - - - - - * * | - - - * - * | <-- |jishu:1|CNT10:2|:10
LC82 -> - - - - - - - - - - - - - - * * | - - - * - * | <-- |jishu:1|CNT10:3|:10
LC36 -> - - - - - - * * * * - - - - - - | - - - * - - | <-- |KEY:7|:3
LC74 -> - - - - - - - - - - - - - - * * | - * * * * * | <-- |MULX:3|:24
LC71 -> - - - - - - - - - - - - - - * * | - * * * * * | <-- |MULX:3|:26
LC66 -> - - - - - - - - - - - - - - * * | - * * * * * | <-- |MULX:3|:28
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\18052034\d1\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------------- LC74 |MULX:3|:24
| +----------------------------- LC71 |MULX:3|:26
| | +--------------------------- LC66 |MULX:3|:28
| | | +------------------------- LC68 |MULX:3|~450~1~2
| | | | +----------------------- LC76 |MULX:3|~450~1~3
| | | | | +--------------------- LC70 |MULX:3|~450~1
| | | | | | +------------------- LC73 |MULX:3|~492~1~2
| | | | | | | +----------------- LC78 |MULX:3|~492~1
| | | | | | | | +--------------- LC69 q0
| | | | | | | | | +------------- LC75 q1
| | | | | | | | | | +----------- LC77 q2
| | | | | | | | | | | +--------- LC80 q3
| | | | | | | | | | | | +------- LC65 q4
| | | | | | | | | | | | | +----- LC67 q5
| | | | | | | | | | | | | | +--- LC72 q6
| | | | | | | | | | | | | | | +- LC79 |SEG7:2|~331~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'E':
LC74 -> * * * * * * * * - - - - - - - - | - * * * * * | <-- |MULX:3|:24
LC71 -> * * * * * * * * - - - - - - - - | - * * * * * | <-- |MULX:3|:26
LC66 -> * * * * * * * * - - - - - - - - | - * * * * * | <-- |MULX:3|:28
LC68 -> - - - - * - - - - - - - - - - - | - - - - * - | <-- |MULX:3|~450~1~2
LC76 -> - - - - - * - - - - - - - - - - | - - - - * - | <-- |MULX:3|~450~1~3
LC70 -> - - - * * * - - * * * * * * * * | - - - - * - | <-- |MULX:3|~450~1
LC73 -> - - - - - - - * - - - - - - - - | - - - - * - | <-- |MULX:3|~492~1~2
LC78 -> - - - - - - * * * * * * * * * * | - - - - * - | <-- |MULX:3|~492~1
LC79 -> - - - - - - - - - - - - - - * - | - - - - * - | <-- |SEG7:2|~331~1
Pin
67 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -