fm.hier_info

VHDL编写的驱动DDS

|FM
wclk <= dds:inst.dds_wclk
clk => dds:inst.clk
fqud <= dds:inst.dds_fqud
reset <= dds:inst.dds_reset
div_clk <= dds:inst.div_clk
address[0] <= lpm_counter0:inst2.q[0]
address[1] <= lpm_counter0:inst2.q[1]
address[2] <= lpm_counter0:inst2.q[2]
address[3] <= lpm_counter0:inst2.q[3]
address[4] <= lpm_counter0:inst2.q[4]
address[5] <= lpm_counter0:inst2.q[5]
address[6] <= lpm_counter0:inst2.q[6]
address[7] <= lpm_counter0:inst2.q[7]
data_out[0] <= dds:inst.dds_data[0]
data_out[1] <= dds:inst.dds_data[1]
data_out[2] <= dds:inst.dds_data[2]
data_out[3] <= dds:inst.dds_data[3]
data_out[4] <= dds:inst.dds_data[4]
data_out[5] <= dds:inst.dds_data[5]
data_out[6] <= dds:inst.dds_data[6]
data_out[7] <= dds:inst.dds_data[7]
datain[0] <= lpm_rom0:inst1.q[0]
datain[1] <= lpm_rom0:inst1.q[1]
datain[2] <= lpm_rom0:inst1.q[2]
datain[3] <= lpm_rom0:inst1.q[3]
datain[4] <= lpm_rom0:inst1.q[4]
datain[5] <= lpm_rom0:inst1.q[5]
datain[6] <= lpm_rom0:inst1.q[6]
datain[7] <= lpm_rom0:inst1.q[7]
datain[8] <= lpm_rom0:inst1.q[8]
datain[9] <= lpm_rom0:inst1.q[9]
datain[10] <= lpm_rom0:inst1.q[10]
datain[11] <= lpm_rom0:inst1.q[11]
datain[12] <= lpm_rom0:inst1.q[12]
datain[13] <= lpm_rom0:inst1.q[13]
datain[14] <= lpm_rom0:inst1.q[14]
datain[15] <= lpm_rom0:inst1.q[15]
datain[16] <= lpm_rom0:inst1.q[16]
datain[17] <= lpm_rom0:inst1.q[17]
datain[18] <= lpm_rom0:inst1.q[18]
datain[19] <= lpm_rom0:inst1.q[19]
datain[20] <= lpm_rom0:inst1.q[20]
datain[21] <= lpm_rom0:inst1.q[21]
datain[22] <= lpm_rom0:inst1.q[22]
datain[23] <= lpm_rom0:inst1.q[23]
datain[24] <= lpm_rom0:inst1.q[24]
datain[25] <= lpm_rom0:inst1.q[25]
datain[26] <= lpm_rom0:inst1.q[26]
datain[27] <= lpm_rom0:inst1.q[27]
datain[28] <= lpm_rom0:inst1.q[28]
datain[29] <= lpm_rom0:inst1.q[29]
datain[30] <= lpm_rom0:inst1.q[30]
datain[31] <= lpm_rom0:inst1.q[31]
dir[0] <= dds:inst.dir[0]
dir[1] <= dds:inst.dir[1]
oe[0] <= dds:inst.oe[0]
oe[1] <= dds:inst.oe[1]


|FM|dds:inst
clk => clkdiv.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
dds_datain[0] => data_reg[0].DATAIN
dds_datain[1] => data_reg[1].DATAIN
dds_datain[2] => data_reg[2].DATAIN
dds_datain[3] => data_reg[3].DATAIN
dds_datain[4] => data_reg[4].DATAIN
dds_datain[5] => data_reg[5].DATAIN
dds_datain[6] => data_reg[6].DATAIN
dds_datain[7] => data_reg[7].DATAIN
dds_datain[8] => data_reg[8].DATAIN
dds_datain[9] => data_reg[9].DATAIN
dds_datain[10] => data_reg[10].DATAIN
dds_datain[11] => data_reg[11].DATAIN
dds_datain[12] => data_reg[12].DATAIN
dds_datain[13] => data_reg[13].DATAIN
dds_datain[14] => data_reg[14].DATAIN
dds_datain[15] => data_reg[15].DATAIN
dds_datain[16] => data_reg[16].DATAIN
dds_datain[17] => data_reg[17].DATAIN
dds_datain[18] => data_reg[18].DATAIN
dds_datain[19] => data_reg[19].DATAIN
dds_datain[20] => data_reg[20].DATAIN
dds_datain[21] => data_reg[21].DATAIN
dds_datain[22] => data_reg[22].DATAIN
dds_datain[23] => data_reg[23].DATAIN
dds_datain[24] => data_reg[24].DATAIN
dds_datain[25] => data_reg[25].DATAIN
dds_datain[26] => data_reg[26].DATAIN
dds_datain[27] => data_reg[27].DATAIN
dds_datain[28] => data_reg[28].DATAIN
dds_datain[29] => data_reg[29].DATAIN
dds_datain[30] => data_reg[30].DATAIN
dds_datain[31] => data_reg[31].DATAIN
dds_wclk <= dds_wclk~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_fqud <= dds_fqud~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_reset <= <GND>
dir[0] <= <GND>
dir[1] <= <GND>
oe[0] <= <GND>
oe[1] <= <GND>
dds_data[0] <= dds_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[1] <= dds_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[2] <= dds_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[3] <= dds_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[4] <= dds_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[5] <= dds_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[6] <= dds_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dds_data[7] <= dds_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
div_clk <= clkdiv.DB_MAX_OUTPUT_PORT_TYPE


|FM|lpm_rom0:inst1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]
q[16] <= altsyncram:altsyncram_component.q_a[16]
q[17] <= altsyncram:altsyncram_component.q_a[17]
q[18] <= altsyncram:altsyncram_component.q_a[18]
q[19] <= altsyncram:altsyncram_component.q_a[19]
q[20] <= altsyncram:altsyncram_component.q_a[20]
q[21] <= altsyncram:altsyncram_component.q_a[21]
q[22] <= altsyncram:altsyncram_component.q_a[22]
q[23] <= altsyncram:altsyncram_component.q_a[23]
q[24] <= altsyncram:altsyncram_component.q_a[24]
q[25] <= altsyncram:altsyncram_component.q_a[25]
q[26] <= altsyncram:altsyncram_component.q_a[26]
q[27] <= altsyncram:altsyncram_component.q_a[27]
q[28] <= altsyncram:altsyncram_component.q_a[28]
q[29] <= altsyncram:altsyncram_component.q_a[29]
q[30] <= altsyncram:altsyncram_component.q_a[30]
q[31] <= altsyncram:altsyncram_component.q_a[31]


|FM|lpm_rom0:inst1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_a[24] => ~NO_FANOUT~
data_a[25] => ~NO_FANOUT~
data_a[26] => ~NO_FANOUT~
data_a[27] => ~NO_FANOUT~
data_a[28] => ~NO_FANOUT~
data_a[29] => ~NO_FANOUT~
data_a[30] => ~NO_FANOUT~
data_a[31] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_jm21:auto_generated.address_a[0]
address_a[1] => altsyncram_jm21:auto_generated.address_a[1]
address_a[2] => altsyncram_jm21:auto_generated.address_a[2]
address_a[3] => altsyncram_jm21:auto_generated.address_a[3]
address_a[4] => altsyncram_jm21:auto_generated.address_a[4]
address_a[5] => altsyncram_jm21:auto_generated.address_a[5]
address_a[6] => altsyncram_jm21:auto_generated.address_a[6]
address_a[7] => altsyncram_jm21:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_jm21:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_jm21:auto_generated.q_a[0]
q_a[1] <= altsyncram_jm21:auto_generated.q_a[1]
q_a[2] <= altsyncram_jm21:auto_generated.q_a[2]
q_a[3] <= altsyncram_jm21:auto_generated.q_a[3]
q_a[4] <= altsyncram_jm21:auto_generated.q_a[4]
q_a[5] <= altsyncram_jm21:auto_generated.q_a[5]
q_a[6] <= altsyncram_jm21:auto_generated.q_a[6]
q_a[7] <= altsyncram_jm21:auto_generated.q_a[7]
q_a[8] <= altsyncram_jm21:auto_generated.q_a[8]
q_a[9] <= altsyncram_jm21:auto_generated.q_a[9]
q_a[10] <= altsyncram_jm21:auto_generated.q_a[10]
q_a[11] <= altsyncram_jm21:auto_generated.q_a[11]
q_a[12] <= altsyncram_jm21:auto_generated.q_a[12]
q_a[13] <= altsyncram_jm21:auto_generated.q_a[13]
q_a[14] <= altsyncram_jm21:auto_generated.q_a[14]
q_a[15] <= altsyncram_jm21:auto_generated.q_a[15]
q_a[16] <= altsyncram_jm21:auto_generated.q_a[16]
q_a[17] <= altsyncram_jm21:auto_generated.q_a[17]
q_a[18] <= altsyncram_jm21:auto_generated.q_a[18]
q_a[19] <= altsyncram_jm21:auto_generated.q_a[19]
q_a[20] <= altsyncram_jm21:auto_generated.q_a[20]
q_a[21] <= altsyncram_jm21:auto_generated.q_a[21]
q_a[22] <= altsyncram_jm21:auto_generated.q_a[22]
q_a[23] <= altsyncram_jm21:auto_generated.q_a[23]
q_a[24] <= altsyncram_jm21:auto_generated.q_a[24]
q_a[25] <= altsyncram_jm21:auto_generated.q_a[25]
q_a[26] <= altsyncram_jm21:auto_generated.q_a[26]
q_a[27] <= altsyncram_jm21:auto_generated.q_a[27]
q_a[28] <= altsyncram_jm21:auto_generated.q_a[28]
q_a[29] <= altsyncram_jm21:auto_generated.q_a[29]
q_a[30] <= altsyncram_jm21:auto_generated.q_a[30]
q_a[31] <= altsyncram_jm21:auto_generated.q_a[31]
q_b[0] <= <GND>


|FM|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2