range.v

采用冒泡排序的方式在verilog中实现

module range(ra,rb,rc,rd,a,b,c,d);
output[7:0] ra,rb,rc,rd;
input[7:0] a,b,c,d;
reg[7:0] ra,rb,rc,rd;
reg[7:0] memo[3:0];
integer i,j;
task exchange;
inout x,y;
reg temp;
begin
if(x>y)
 begin
    temp=x;
    x=y;
    y=temp;
end
end
endtask
  
always @(a or b or c or d)
 fork
  memo[0]=a;
  memo[1]=b;
  memo[2]=c;
  memo[3]=d;
 join
 
 always @(a or b or c or d)
 begin
 for(i=0;i<4;i=i+1)
  begin
       for(j=0;j<3-i;j=j+1)
   exchange(memo[j+1],memo[j]);
   end
  ra=memo[0];
  rb=memo[1];
  rc=memo[2];
  rd=memo[3];
   end
   endmodule