range_tb.v

采用冒泡排序的方式在verilog中实现

module std_tb;
reg [7:0] a,b,c,d;
wire [7:0]  ra,rb,rc,rd;
 range sort4(ra,rb,rc,rd,a,b,c,d);
initial
 fork
  a=15;
  b=56;
  c=23;
  d=24;
  #50 a=5;
  #50 b=10;
  #50 c=1;
  #50 d=4;
  #86 a=15;
  #15 b=51;
  #87 c=86;
  #59 d=23;
  #100 $stop;
  join
  endmodule