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采用冒泡排序的方式在verilog中实现

module sort4(clk,reset,ra,rb,rc,rd,a);
output [7:0] ra,rb,rc,rd;
input [7:0] a;
input clk,reset;

reg [7:0] ra,rb,rc,rd;
reg [7:0] memo[3:0];
integer i,j;
initial i=0;
initial j=0;

task exchange;  
inout[7:0] x,y;  
reg[7:0] tmp;
   if(x>y)  
     begin
       tmp=x;  
       x=y;
       y=tmp;
     end
endtask

always @(posedge clk)
begin
 if(!reset)
  begin
  memo[0]<=8'b00000000;
  memo[1]<=8'b00000000;
  memo[2]<=8'b00000000;
  memo[3]<=8'b00000000;
 end
else
  if(clk)
  begin
   memo[i]=a;
    i=i+1;
   if(i==4)
    i=0;
end
always 
 begin
   if(i==4)
   begin
    exchange(memo[j+1],memo[j]);
    j=j+1;
   
   ra=memo[0];
   rb=memo[1];
   rc=memo[2];
   rd=memo[3];
   if(j==3) j=0;
   end
   end
  end
endmodule