ad9852.v

数字频率合成器芯片AD9852 的配置文件

附录B  AD9852配置RTL代码
//configration for the AD9852
//module function:
// the module is designed to initialize AD9852 to work at the mode of BPSK
//module ref_clk()  
`timescale 1ns/100ps
module
serial(reset,fpga_clk,ms_rst,sclk,cs,sdio,io_rst,ud_clk,refclk1,refclk2,pmode,fdata);
   input reset;    //low active
   input fpga_clk; //fpga clk 20M
   output ms_rst;  //reset signal with high active
   output sclk;    //serial data clk 9.375M
   output cs;      //chip select with low active
   output sdio;    //serial data input or output,here we use it as the output of the module and the input of AD9852
   output io_rst;
   output ud_clk;  //clk used to transfer the data from io_buff to registor
   output refclk1;  //20M refclk for ad8952
   output refclk2;
   output pmode;   //the s/p select signal which select serial mode with the logic low 
   output fdata;
  
   reg ms_rst;
   reg sclk;
   reg cs;
   reg io_rst;
   reg ud_clk;
   reg fdata;

   wire sclk_con;
   reg refclk_en;  //refclk enable with hign active
   reg sclk_buff_t;
   reg [1:0]state;
   reg flag;
   reg [1:0]i;
   reg [7:0]counter;
   wire clk_40;	
   wire clk_16;
   reg clk_8;
   reg clk_4;
   reg clk_2;
   reg rst_c;
  // wire restart_c;
   //wire dump_c;   
   integer counter_clk;
   parameter  read=2'b00,
			  idle1=2'b01,
			  idle2=2'b10,
			  finish=2'b11;
    assign refclk1 = refclk_en?fpga_clk:1'bz;
    assign refclk2 = refclk_en?(~fpga_clk):1'bz;
	assign pmode = 1'b0;
   //pll10 p1(.inclk0(fpga_clk),.c0(sclk));        //9.375M sclk_buff;
	assign sclk_con = ~sclk;
	//assign restart_c = 1'b0;
	//assign fdata = clk_4;
	//pll16 p2(.inclk0(fpga_clk),.c0(clk_16));			//16M 
	pll_40 p1(.inclk0(fpga_clk),.c0(clk_40)); 
	rom r1(.address(counter),.clock(sclk_con),.q(sdio));
	//code_gen c1(.clk(clk_4),.rst(rst_c),.enable(clk_4),.restart(restart_c),.dump(dump_c),.CA_code(fdata)); 
	always@(posedge fpga_clk)
	sclk_buff_t <= ~sclk_buff_t;
	always@(posedge sclk_buff_t)
	sclk <= ~sclk;
	/*always@(posedge clk_16)
	if (counter_clk<1)
		counter_clk = counter_clk + 1;
	else
	begin
		clk_4 <= ~clk_4;
		counter_clk = 0;
	end
	always@(posedge clk_4)
	clk_2 <= ~clk_2;*/
	always@(posedge clk_40)
	if (counter_clk<18)
		counter_clk = counter_clk + 1;
	else
	begin
		fdata <= ~fdata;
		counter_clk = 0;
	end
   always@(negedge reset or posedge sclk)
   begin
       if(!reset)
		begin
       	 i <= 2'b0;
		end
       else 
		begin
			if(i!=3)
			begin
				i <= i + 2'b01;
			end	
		end
   end
   always@(i)
	begin
		if(i==0)
		ms_rst = 1'b0;
		else if(i==1)
		ms_rst = 1'b1; 
		else if(i==2)
		ms_rst = 1'b0;
	end       
   always@(negedge sclk or negedge reset)// or posedge ms_rst)
	if(!reset)
	begin
	  cs <= 1'b1;		
      ud_clk <= 1'b0;	
      io_rst <= 1'b1;	
      refclk_en <= 1'b0;
	  //rst_c <= 1'b0;
     // fdata <= 1'b1;	
	  flag <= 1'b0;	 
	  state <= finish;
	end	
	else if(ms_rst)
	begin
	  // rst_c <= 1'b1;
 	   flag <= 1'b1;
	end
	else 
	begin
					   if(flag)
					   begin 
					   	   state <= read;
						   flag <= 1'b0;
						   counter <= 0;
					   end
					   else
					   begin
					      case(state)
						   read:begin
								cs <= 1'b0;
								io_rst <= 1'b0;
								ud_clk <= 1'b0;  		
								counter <= counter + 8'b00000001;
								if(counter==39)
								begin
									state <= idle1;
								end
								else if(counter==119||counter==143)
									state <= idle2;
						  	  	end
						   idle1:begin
									cs <= 1'b1;
									io_rst <= 1'b1;
									refclk_en <= 1'b1;
									state <= read;
								end
						   idle2:begin
									cs <= 1'b1;
									io_rst <= 1'b1;
									ud_clk <= 1'b1;
									if(counter==120)
									begin
										state <= read;
									end
									else if(counter==144)
									begin
										state <= finish;
									end
								end
						   finish:begin
									ud_clk <= 1'b0;
									state <= finish;
								end
						  endcase
					   end 					 
	end		
endmodule