tap.vhd

自适应滤波器adaptive的vhdl实现的源代码。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use Work.kang.all;
entity tap is
Port ( clk : in std_logic;
rst : in std_logic;
Write_Data : in std_logic_vector(14 downto 0);
Bank_Sel : in std_logic;
Tap_Sel : in std_logic;
Write_Addr : in std_logic_vector(3 downto 0);
Read_Data : in std_logic_vector(3 downto 0);
Data_Valid : out std_logic;
Tap_out : out std_logic_vector(23 downto 0);
NT_tsb : out std_logic_vector(3 downto 0) );
end tap;
-----------------------------------------------------------------------
architecture Structural of tap is

signal tsb_out : std_logic_vector(3 downto 0);
signal mux_1_out : std_logic_vector(3 downto 0);
signal mux_2_out : std_logic_vector(3 downto 0);
signal mux_3_out : std_logic_vector(14 downto 0);
signal First_oct : std_logic;
signal lut1_we : std_logic;
signal lut2_we : std_logic;
signal lut_1_out : std_logic_vector(14 downto 0);
signal lut_2_out : std_logic_vector(14 downto 0);
------------------------------------------------------------------------------
begin
TSB_1 : tsb port map(clk, Read_Data, tsb_out, First_oct);
--------------------- Partial Product Multiplier Section ----------------------
MUX_1 :
with Bank_Sel select
mux_1_out <= Write_Addr when '0',
tsb_out when others;
MUX_2 :
with Bank_Sel select
mux_2_out <= Write_Addr when '1',
tsb_out when others;
lut1_we <= not Bank_sel and Tap_Sel;
lut2_we <= Bank_sel and Tap_Sel;
LUT_1 : tap_lut port map(clk, lut1_we, Write_Data, mux_1_out, lut_1_out);
LUT_2 : tap_lut port map(clk, lut2_we, Write_Data, mux_2_out, lut_2_out);
------------------------- Scaling Accumulator Section --------------------------
MUX_3 : mux_reg15 port map(clk, rst, Bank_Sel, lut_1_out, lut_2_out, mux_3_out);
ADDER : pp_adder port map(clk,rst,First_oct,Data_Valid,mux_3_out,Tap_out);
NT_tsb <= tsb_out;
end Structural;