mux_reg15.vhd

自适应滤波器adaptive的vhdl实现的源代码。

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_reg15 is
Port ( clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
mux_in15a : in std_logic_vector(14 downto 0);
mux_in15b : in std_logic_vector(14 downto 0);
mux_out15 : out std_logic_vector(14 downto 0) );
end ;

-- mux_reg15 Component
architecture Behavioral of mux_reg15 is
signal mux_out15_sig : std_logic_vector(14 downto 0);
begin
with sel select
mux_out15_sig <= mux_in15a when '1',
mux_in15b when others;
REG: process(clk,rst)
begin
if rst = '1' then
mux_out15 <= (others => '0');
elsif clk'event and clk = '1' then
mux_out15 <= mux_out15_sig;
end if;
end process;
end Behavioral;