pp_adder.vhd

自适应滤波器adaptive的vhdl实现的源代码。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pp_adder is
Port ( clk : in std_logic;
rst : in std_logic;
f_oct : in std_logic;
valid : out std_logic;
input : in std_logic_vector(14 downto 0);
output : out std_logic_vector(23 downto 0) );
end ;

--pp_adder Component
architecture Behavioral of pp_adder is
signal f_o_delay : std_logic;
signal Adder_sig : std_logic_vector(17 downto 0);
signal LSB_0 : std_logic_vector(2 downto 0);
signal LSB_1 : std_logic_vector(2 downto 0);
signal LSB_2 : std_logic_vector(2 downto 0);
begin
process(clk, input, rst)
variable s_extend, a_extend : std_logic_vector(2 downto 0);
begin
if rst = '1' then
Adder_sig <= (others => '0');
LSB_0 <= (others => '0');
LSB_1 <= (others => '0');
LSB_2 <= (others => '0');
elsif clk'event and clk = '1' then
-- Sign extend for input and Adder_sig
for i in 2 downto 0 loop
s_extend(i) := input(14);
a_extend(i) := Adder_sig(17);
end loop;
f_o_delay <= f_oct;
if f_o_delay = '1' then
Adder_sig <= ( s_extend & input );
LSB_0 <= (others => '0');
LSB_1 <= (others => '0');
LSB_2 <= input(2 downto 0);
valid <= '1';
else
Adder_sig<=(a_extend&Adder_sig(17 downto 3))+(s_extend & input);
LSB_0 <= LSB_1;
LSB_1 <= LSB_2;
LSB_2 <= Adder_sig(2 downto 0);
valid <= '0';
end if;
output <= Adder_sig(14 downto 0) & LSB_2 & LSB_1 & LSB_0;
end if;
end process;
end Behavioral;