clock_gen.vhd

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--      DDR_Clkn                -- DDR inverted clock output(s)
--
---------------------------------------------------------------------------

-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------

entity clock_gen is
  generic (
        C_NUM_CLK_PAIRS     : integer range 1 to 4 := 1;
        C_FAMILY            : string := "virtex2"
        );
  port (
        Sys_clk             : in  std_logic;
        Sys_clk_n           : in  std_logic;
        Clk90_in            : in  std_logic;
        Clk90_in_n          : in  std_logic;
        DDR_Clk90_in        : in  std_logic;
        DDR_Clk90_in_n      : in  std_logic;
        Clk                 : out std_logic;
        Clk_n               : out std_logic;
        Clk90               : out std_logic;
        Clk90_n             : out std_logic;
        Clk_ddr_rddata      : out std_logic;
        Clk_ddr_rddata_n    : out std_logic;
        DDR_Clk             : out std_logic_vector(0 to C_NUM_CLK_PAIRS-1);
        DDR_Clkn            : out std_logic_vector(0 to C_NUM_CLK_PAIRS-1)
   
        );
        
end entity clock_gen;

-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------

architecture imp of clock_gen is

-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------

begin  
-- assign output signals
Clk <= Sys_clk;
Clk_n <= Sys_clk_n;
Clk90 <= Clk90_in;
Clk90_n <= Clk90_in_n;
Clk_ddr_rddata <= DDR_Clk90_in;
Clk_ddr_rddata_n <= DDR_Clk90_in_n;

----------------------------------------------------------------------------------
-- For all devices except Virtex4, instantiate DDR registers with IOB attributes
-- Generate statement: if C_FAMILY is not equal to Virtex4 (ie. all other devices)
----------------------------------------------------------------------------------
NOT_VIRTEX4_IOREGS: if not (equalIgnoreCase(C_FAMILY, "virtex4")) generate

begin

    -------------------------------------------------------------------------------
    -- DDR Clock Outputs 
    -------------------------------------------------------------------------------
    -- use DDR I/O registers with Clk90 to generate DDR Clk and CLkn outputs
    -- DDR Clk and Clkn are generated from Clk90 so it is centered in the data

    GEN_CLK_PAIR_N : for i in 0 to C_NUM_CLK_PAIRS-1 generate
    
    attribute IOB : string;
    attribute IOB of DDR_CLK_REG_I  : label is "true";
    attribute IOB of DDR_CLKN_REG_I : label is "true";

    begin

        DDR_CLK_REG_I: FDDRRSE
          port map (
            Q   => DDR_Clk(i),                  --[out]
            C0  => Clk90_in,                    --[in]
            C1  => Clk90_in_n,                  --[in]
            CE  => '1',                         --[in]
            D0  => '1',                         --[in]
            D1  => '0',                         --[in]
            R   => '0',                         --[in]
            S   => '0'                          --[in]
          );

        DDR_CLKN_REG_I: FDDRRSE
          port map (
            Q   => DDR_Clkn(i),                 --[out]
            C0  => Clk90_in,                    --[in]
            C1  => Clk90_in_n,                  --[in]
            CE  => '1',                         --[in]
            D0  => '0',                         --[in]
            D1  => '1',                         --[in]
            R   => '0',                         --[in]
            S   => '0'                          --[in]
          );
          
    end generate GEN_CLK_PAIR_N;

end generate NOT_VIRTEX4_IOREGS;

----------------------------------------------------------------------------------
-- For Virtex4, instantiate IDDR and ODDR registers
-- IDDR and ODDR are defined UNISIM components
-- Generate statement: if C_FAMILY is equal to Virtex4
----------------------------------------------------------------------------------
VIRTEX4_IOREGS: if (equalIgnoreCase(C_FAMILY, "virtex4")) generate

-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
-- Used for generic mapping on ODDR and IDDR components
constant DDR_CLK_OPPOSITE_EDGE : string := "OPPOSITE_EDGE";
constant INIT_0         : bit := '0';
constant SRTYPE_SYNC    : string := "SYNC";

begin

    -------------------------------------------------------------------------------
    -- DDR Clock Outputs 
    -------------------------------------------------------------------------------
    -- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
    -- use DDR I/O registers with CLk90 to generate DDR Clk and CLkn outputs
    -- DDR Clk and Clkn are generated from CLK90 so it is centered in the data
    
    GEN_CLK_PAIR_N : for i in 0 to C_NUM_CLK_PAIRS-1 generate

        -- Use ODDR register to generate DDR_Clk
        DDR_CLK_REG_V4_I: ODDR
        generic map (
            DDR_CLK_EDGE    => DDR_CLK_OPPOSITE_EDGE,   -- use clk 180
            INIT            => INIT_0,                  -- power up low
            SRTYPE          => SRTYPE_SYNC              -- syncronous set & reset  
            )
        port map (
            Q   => DDR_Clk(i)       ,           --[out]
            C   => Clk90_in         ,           --[in]
            CE  => '1'              ,           --[in]
            D1  => '1'              ,           --[in]
            D2  => '0'              ,           --[in]
            R   => '0'              ,           --[in]
            S   => '0'                          --[in]
            );

        -- Use ODDR register to generate DDR_Clkn
        DDR_CLKN_REG_V4_I: ODDR
        generic map (
            DDR_CLK_EDGE    => DDR_CLK_OPPOSITE_EDGE,   -- use clk 180
            INIT            => INIT_0,                  -- power up low
            SRTYPE          => SRTYPE_SYNC              -- syncronous set & reset  
            )
        port map (
            Q   => DDR_Clkn(i)      ,           --[out]
            C   => Clk90_in         ,           --[in]
            CE  => '1'              ,           --[in]
            D1  => '0'              ,           --[in]
            D2  => '1'              ,           --[in]
            R   => '0'              ,           --[in]
            S   => '0'                          --[in]
            );
    
    end generate GEN_CLK_PAIR_N;

end generate VIRTEX4_IOREGS;

end imp;