clock_gen.vhd

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-------------------------------------------------------------------------------
-- $Id: clock_gen.vhd,v 1.5 2004/08/09 22:17:53 jennj Exp $
-------------------------------------------------------------------------------
-- clock_gen.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  function and run at speed according to the datasheet                 **
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--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
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--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        clock_gen.vhd
-- Version:         v1.10a
-- Description:     This file contains the logic to generate the DDR output
--                  clocks, DDR_Clk and DDR_Clkn.
--
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--                  ddr_controller.vhd
--                      -- read_data_path.vhd
--                      -- data_statemachine.vhd
--                      -- command_statemachine.vhd
--                      -- init_statemachine.vhd
--                      -- counters.vhd
--                      -- io_registers.vhd
--                      -- clock_gen.vhd
--                      -- ipic_if.vhd
--
-------------------------------------------------------------------------------
-- Author:          ALS
-- History:
-- ALS              05/15/02    First Version
--
-- ALS              06/03/02
-- ^^^^^^
-- Registers that generate the DDR clock are no longer reset because the clock
-- feeds back to the DCM and violates the max clock value if a reset occurs
-- after power-up. Also, added BEGIN statement to generates.
-- ~~~~~~
-- ALS              06/12/02
-- Will use the clk90 output of the ddr dcm to capture ddr read data.
--
-- ALS              06/15/02
-- ^^^^^^
-- Test version - generation of DDR clock outputs has been moved out of 
-- DDRCLK_GEN generate so that the DDR DCM can be put at the system level
-- for experimentation.
-- ~~~~~~~
-- ALS              07/12/02
-- ^^^^^^
-- Renamed C_INCLUDE_CLK90_GEN to C_INCLUDE_CLK90_DCM for clarity. Added
-- C_INCLUDE_DDRCLK_DCM to separate the inclusion of the DDR DCM logic and the
-- output DDR registers that generate the DDR clock outputs.
-- ~~~~~~
--  JLJ             02/18/04
-- ^^^^^^
-- Added the following inputs: Sys_clk_n, Clk90_in_n, & DDR_Clk_in_n 
-- Added the following outputs: Clk_n, Clk90_n, & Clk_ddr_rddata_n
-- This update requires global inversion on clock inputs to prevent any
-- duty cycle distortion as system frequencies increase. 
-- ~~~~~~
--  JLJ             02/25/04
-- ^^^^^^
-- Create multiple DDR clock pairs to support clocking requirements
-- of certain DDR SDRAM DIMM vendors. Added support for up to 3 differential
-- DDR clock pairs.  Renamed DDR_Clk and DDR_Clkn to DDR_Clk0 and DDR_Clk0n.
-- Added ports DDR_Clk1, DDR_Clk1n, DDR_Clk2, DDR_Clk2n.
-- ~~~~~~
--  JLJ             03/18/04
-- ^^^^^^
--  Updated to version v1.10a.  Added support for Virtex4 (uses family.vhd in
--  proc_common_v2_00_a).  Also updated to proc_common_v2_00_a.
-- ~~~~~~
--  JLJ             04/06/04
-- ^^^^^^
--  Added parameter, C_NUM_CLK_PAIRS for the number of differential DDR clock
--  pairs needed in design.  Renamed DDR_Clk0, DDR_Clk0n, DDR_Clk1, DDR_Clk1n, 
--  DDR_Clk2, & DDR_Clk2n to DDR_Clk (0:C_NUM_CLK_PAIRS-1) and 
--  DDR_Clkn (0:C_NUM_CLK_PAIRS-1).
-- ~~~~~~
--  JLJ             05/05/04
-- ^^^^^^
--  Add component declaration for Virtex-4 primitive: ODDR.
-- ~~~~~~
--  JLJ             08/09/04
-- ^^^^^^
--  Remove component declaration for Virtex-4 primitives: IDDR & ODDR.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.family.all;
use proc_common_v2_00_a.all;

library unisim;
use unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Definition of Generics:
--      C_NUM_CLK_PAIRS         -- supported number of DDR clock pairs
--      C_FAMILY                -- target FPGA family type
--
-- Definition of Ports:
--  -- inputs
--      Sys_clk                 -- system clock
--      Sys_clk_n               -- system clock phase shifted by 180 degrees
--      Clk90_in                -- clock 90 input for use if C_INCLUDE_CLK90_DCM=0
--      Clk90_in_n              -- clock 90 input phase shifted by 180 degrees
--      DDR_Clk_in              -- ddr clock input
--      DDR_Clk_in_n            -- ddr clock input phase shifted by 180 degrees
--
--  -- outputs
--      Clk                     -- either SysClk or DCM output
--      Clk_n                   -- either SysClk or DCM output phase shifted by 180
--      Clk90                   -- SysClk with 90 degree phase shift
--      Clk90_n                 -- SysClk with 270 degree phase shift
--      Clk_ddr_rddata          -- DDR clock used to register incoming read data
--      Clk_ddr_rddata_n        -- DDR clock used to register incoming read data shifted by 180
--      DDR_Clk                 -- DDR clock output(s)