📄 io_registers.vhd
字号:
D2 => Write_data_mask(C_DDR_DWIDTH/8+i), --[in]
R => '0', --[in]
S => Rst --[in]
);
-- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
-- DQS is generated from CLK90 so it is centered in the data
-- Assuming pullups are on the board, set DQS based on DQS_setrst
-- and reset based on DQS_rst
DDR_DQS_REG_V4_I: ODDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT => INIT_1, -- power up high
SRTYPE => SRTYPE_SYNC -- syncronous set & reset
)
port map (
Q => DDR_DQS_o(i), --[out]
C => Clk90, --[in]
CE => Write_dqs_en(i), --[in]
D1 => '1', --[in]
D2 => '0', --[in]
R => DQS_rst(i), --[in]
S => DQS_setrst(i) --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQST_REG_I: FDS
port map (
Q => DDR_DQS_t(i), --[out]
C => Clk90, --[in]
D => DQS_oe(i), --[in]
S => '0' --[in]
);
end generate DDR_DMDQS_REG_GEN;
-- If C_INCLUDE_ECC_SUPPORT = 1
-- Include DM_ECC and DQS_ECC I/O registers
W_DQS_ECC_REG: if C_INCLUDE_ECC_SUPPORT = 1 generate
attribute IOB : string;
attribute IOB of DDR_DQST_ECC_REG_I : label is "true"; -- only use for FDR components
begin
-- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
-- use ODDR register to generate DM and DQS
DDR_DM_ECC_REG_V4_I: ODDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT => INIT_1, -- power up high
SRTYPE => SRTYPE_SYNC -- syncronous set & reset
)
port map (
Q => DDR_DM_ECC, --[out]
C => Clk, --[in]
CE => Write_data_ecc_en, --[in]
D1 => Write_data_ecc_mask(0), --[in]
D2 => Write_data_ecc_mask(1), --[in]
R => '0', --[in]
S => Rst --[in]
);
-- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
-- DQS is generated from CLK90 so it is centered in the data
-- Assuming pullups are on the board, set DQS based on DQS_setrst
-- and reset based on DQS_rst
DDR_DQS_ECC_REG_V4_I: ODDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT => INIT_1, -- power up high
SRTYPE => SRTYPE_SYNC -- syncronous set & reset
)
port map (
Q => DDR_DQS_ECC_o, --[out]
C => Clk90, --[in]
CE => Write_dqs_ecc_en, --[in]
D1 => '1', --[in]
D2 => '0', --[in]
R => DQS_ECC_rst, --[in]
S => DQS_ECC_setrst --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQST_ECC_REG_I: FDS
port map (
Q => DDR_DQS_ECC_t, --[out]
C => Clk90, --[in]
D => DQS_ECC_oe, --[in]
S => '0' --[in]
);
end generate W_DQS_ECC_REG;
-- Can use regular registers with attributes for the rest of the control signals
-- DDR address
DDR_ADDR_REG_GEN: for i in 0 to C_DDR_AWIDTH-1 generate
attribute IOB : string;
attribute IOB of DDR_ADDR_REG_I : label is "true";
begin
DDR_ADDR_REG_I: FDR
port map (
Q => DDR_Addr(i), --[out]
C => Clk, --[in]
D => Addr(i), --[in]
R => Rst --[in]
);
end generate DDR_ADDR_REG_GEN;
-- DDR Bank Address
DDR_BANKADDR_REG_GEN: for i in 0 to C_DDR_BANK_AWIDTH-1 generate
attribute IOB : string;
attribute IOB of DDR_BANKADDR_REG_I : label is "true";
begin
DDR_BANKADDR_REG_I: FDR
port map (
Q => DDR_BankAddr(i), --[out]
C => Clk, --[in]
D => BankAddr(i), --[in]
R => Rst --[in]
);
end generate DDR_BANKADDR_REG_GEN;
-- DDR CSn generate
DDR_CSN_REG_GEN: for i in 0 to C_NUM_BANKS_MEM-1 generate
attribute IOB : string;
attribute IOB of DDR_CSN_REG_I : label is "true";
begin
DDR_CSN_REG_I: FDS
port map (
Q => DDR_CSn(i), --[out]
C => Clk, --[in]
D => CSn(i), --[in]
S => Rst --[in]
);
end generate DDR_CSN_REG_GEN;
-- DDR RASn, CASn, and WEn
DDR_RASN_REG: FDS
port map (
Q => DDR_RASn,--[out]
C => Clk, --[in]
D => RASn, --[in]
S => Rst --[in]
);
DDR_CASN_REG: FDS
port map (
Q => DDR_CASn,--[out]
C => Clk, --[in]
D => CASn, --[in]
S => Rst --[in]
);
DDR_WEN_REG: FDS
port map (
Q => DDR_WEn, --[out]
C => Clk, --[in]
D => WEn, --[in]
S => Rst --[in]
);
-------------------------------------------------------------------------------
-- IOB input DDR registers
-------------------------------------------------------------------------------
-- First synchronize the read data enable signal
RD_DATAEN_SYNC_REG: FDC
port map (
Q => ddr_read_data_en_i, --[out]
C => Clk_ddr_rddata, --[in]
CLR => Rst, --[in]
D => Read_data_en --[in]
);
-- Synchronize the read dqs ce signal
RD_DQSCE_SYNC_REG: FDC
port map (
Q => ddr_read_dqs_ce, --[out]
C => Clk_ddr_rddata, --[in]
CLR => Rst, --[in]
D => Read_dqs_ce --[in]
);
INPUT_DDR_REGS_GEN: for i in 0 to C_DDR_DWIDTH -1 generate
begin
-- New for Virtex4
-- Use IDDR component with asynchronous reset to replace FDCE
-- use async reset since reg is clocked from Clk_ddr_rddata
RDDATA_V4: IDDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT_Q1 => INIT_0, -- power up low
INIT_Q2 => INIT_0, -- power up low
SRTYPE => SRTYPE_ASYNC -- async set & reset
)
port map (
Q1 => DDR_ReadData(i) , --[out]
Q2 => DDR_ReadData(C_DDR_DWIDTH+i) , --[out]
C => Clk_ddr_rddata , --[in]
CE => ddr_read_data_en_i , --[in]
D => DDR_DQ_i(i) , --[in]
R => Rst , --[in]
S => '0' --[in]
);
end generate INPUT_DDR_REGS_GEN;
INPUT_DQS_REG_GEN: for i in 0 to C_DDR_DWIDTH/8-1 generate
attribute IOB : string;
--attribute IOB of RDDQS_REG : label is "true";
attribute IOB of RDDQS_REG : label is "false";
begin
RDDQS_REG: FDCE
port map (
Q => DDR_Read_DQS(i), --[out]
C => Clk_ddr_rddata, --[in]
D => DDR_DQS_i(i), --[in]
CE => ddr_read_dqs_ce, --[in]
CLR => '0' --[in]
);
end generate INPUT_DQS_REG_GEN;
-- Generate to include DQ_ECC and DQS_ECC input registers
W_ECC_IN_REGS: if C_INCLUDE_ECC_SUPPORT = 1 generate
attribute IOB : string;
-- attribute IOB of RDDQS_ECC_REG : label is "true";
attribute IOB of RDDQS_ECC_REG : label is "false";
begin
INPUT_DDR_ECC_REGS_GEN: for i in 0 to NUM_ECC_BITS -1 generate
begin
-- Use IDDR component with asynchronous reset to replace FDCE
-- use async reset since reg is clocked from Clk_ddr_rddata
RDDATA_ECC_V4: IDDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT_Q1 => INIT_0, -- power up low
INIT_Q2 => INIT_0, -- power up low
SRTYPE => SRTYPE_ASYNC -- async set & reset
)
port map (
Q1 => DDR_ReadData_ECC(i) , --[out]
Q2 => DDR_ReadData_ECC(NUM_ECC_BITS+i) , --[out]
C => Clk_ddr_rddata , --[in]
CE => ddr_read_data_en_i , --[in]
D => DDR_DQ_ECC_i(i) , --[in]
R => Rst , --[in]
S => '0' --[in]
);
end generate INPUT_DDR_ECC_REGS_GEN;
RDDQS_ECC_REG: FDCE
port map (
Q => DDR_Read_DQS_ECC, --[out]
C => Clk_ddr_rddata, --[in]
D => DDR_DQS_ECC_i, --[in]
CE => ddr_read_dqs_ce, --[in]
CLR => '0' --[in]
);
end generate W_ECC_IN_REGS;
end generate VIRTEX4_IOREGS;
end imp;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -