📄 io_registers.vhd
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Q => DDR_CSn(i), --[out]
C => Clk, --[in]
D => CSn(i), --[in]
S => Rst --[in]
);
end generate DDR_CSN_REG_GEN;
-- DDR RASn, CASn, and WEn
DDR_RASN_REG: FDS
port map (
Q => DDR_RASn,--[out]
C => Clk, --[in]
D => RASn, --[in]
S => Rst --[in]
);
DDR_CASN_REG: FDS
port map (
Q => DDR_CASn,--[out]
C => Clk, --[in]
D => CASn, --[in]
S => Rst --[in]
);
DDR_WEN_REG: FDS
port map (
Q => DDR_WEn, --[out]
C => Clk, --[in]
D => WEn, --[in]
S => Rst --[in]
);
-------------------------------------------------------------------------------
-- IOB input DDR registers
-------------------------------------------------------------------------------
-- First synchronize the read data enable signal
RD_DATAEN_SYNC_REG: FDC
port map (
Q => ddr_read_data_en_i, --[out]
C => Clk_ddr_rddata, --[in]
CLR => Rst, --[in]
D => Read_data_en --[in]
);
-- Synchronize the read dqs ce signal
RD_DQSCE_SYNC_REG: FDC
port map (
Q => ddr_read_dqs_ce, --[out]
C => Clk_ddr_rddata, --[in]
CLR => Rst, --[in]
D => Read_dqs_ce --[in]
);
INPUT_DDR_REGS_GEN: for i in 0 to C_DDR_DWIDTH -1 generate
attribute IOB : string;
attribute IOB of RDDATA_HIREG : label is "true";
attribute IOB of RDDATA_LOREG : label is "true";
begin
-- use async reset since reg is clocked from Clk_ddr_rddata
RDDATA_HIREG: FDCE
port map (
Q => DDR_ReadData(i), --[out]
C => Clk_ddr_rddata, --[in]
CE => ddr_read_data_en_i,--[in]
D => DDR_DQ_i(i), --[in]
CLR => Rst --[in]
);
RDDATA_LOREG: FDCE
port map (
Q => DDR_ReadData(C_DDR_DWIDTH+i), --[out]
C => clk_ddr_rddata_n, --[in]
CE => ddr_read_data_en_i, --[in]
D => DDR_DQ_i(i), --[in]
CLR => Rst --[in]
);
end generate INPUT_DDR_REGS_GEN;
-- INPUT_DQS_REG_GEN: for i in 0 to C_DDR_DWIDTH/8-1 generate
-- attribute IOB : string;
-- attribute IOB of RDDQS_REG : label is "true";
-- begin
-- RDDQS_REG: FDCE
-- port map (
-- Q => DDR_Read_DQS(i), --[out]
-- C => Clk_ddr_rddata, --[in]
-- D => DDR_DQS_i(i), --[in]
-- CE => ddr_read_dqs_ce,--[in]
-- CLR => '0' --[in]
-- );
-- end generate INPUT_DQS_REG_GEN;
INPUT_DQS_REG: process(Clk_ddr_rddata)
begin
if Clk_ddr_rddata'event and Clk_ddr_rddata = '1' then
DDR_Read_DQS <= DDR_DQS_i;
-- end if;
end if;
end process;
-- Generate to include DQ_ECC and DQS_ECC input registers
W_ECC_IN_REGS: if C_INCLUDE_ECC_SUPPORT = 1 generate
attribute IOB : string;
attribute IOB of RDDQS_ECC_REG : label is "true";
begin
INPUT_DDR_ECC_REGS_GEN: for i in 0 to NUM_ECC_BITS -1 generate
attribute IOB : string;
attribute IOB of RDDATA_ECC_HIREG : label is "true";
attribute IOB of RDDATA_ECC_LOREG : label is "true";
begin
-- use async reset since reg is clocked from Clk_ddr_rddata
RDDATA_ECC_HIREG: FDCE
port map (
Q => DDR_ReadData_ECC(i), --[out]
C => Clk_ddr_rddata, --[in]
CE => ddr_read_data_en_i, --[in]
D => DDR_DQ_ECC_i(i), --[in]
CLR => Rst --[in]
);
RDDATA_ECC_LOREG: FDCE
port map (
Q => DDR_ReadData_ECC(NUM_ECC_BITS+i),--[out]
C => clk_ddr_rddata_n, --[in]
CE => ddr_read_data_en_i, --[in]
D => DDR_DQ_ECC_i(i), --[in]
CLR => Rst --[in]
);
end generate INPUT_DDR_ECC_REGS_GEN;
RDDQS_ECC_REG: FDCE
port map (
Q => DDR_Read_DQS_ECC, --[out]
C => Clk_ddr_rddata, --[in]
D => DDR_DQS_ECC_i, --[in]
CE => ddr_read_dqs_ce, --[in]
CLR => '0' --[in]
);
end generate W_ECC_IN_REGS;
end generate NOT_VIRTEX4_IOREGS;
----------------------------------------------------------------------------------
-- For Virtex4, instantiate IDDR and ODDR registers
-- IDDR and ODDR are defined UNISIM components
-- Generate statement: if C_FAMILY is equal to Virtex4
----------------------------------------------------------------------------------
VIRTEX4_IOREGS: if (equalIgnoreCase(C_FAMILY, "virtex4")) generate
-----------------------------------------------------------------------------
-- Attribute declarations
-----------------------------------------------------------------------------
attribute IOB : string;
attribute IOB of DDR_RASN_REG : label is "true";
attribute IOB of DDR_CASN_REG : label is "true";
attribute IOB of DDR_WEN_REG : label is "true";
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
-- Used for generic mapping on ODDR and IDDR components
constant DDR_CLK_OPPOSITE_EDGE : string := "OPPOSITE_EDGE";
constant INIT_0 : bit := '0';
constant INIT_1 : bit := '1';
constant SRTYPE_SYNC : string := "SYNC";
constant SRTYPE_ASYNC : string := "ASYNC";
begin
-------------------------------------------------------------------------------
-- Instantiate the IOB Output registers
-------------------------------------------------------------------------------
DDR_DQ_REG_GEN: for i in 0 to C_DDR_DWIDTH-1 generate
attribute IOB : string;
attribute IOB of DDR_DQT_REG_I : label is "true"; -- only use for FDR components
begin
-- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
-- use ODDR register to generate DDR_DQ_o
DDR_DQ_REG_V4_I: ODDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT => INIT_0, -- power up low
SRTYPE => SRTYPE_SYNC -- syncronous set & reset
)
port map (
Q => DDR_DQ_o(i), --[out]
C => Clk, --[in]
CE => Write_data_en, --[in]
D1 => Write_data(i), --[in]
D2 => Write_data(C_DDR_DWIDTH+i), --[in]
R => Rst, --[in]
S => '0' --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQT_REG_I: FDS
port map (
Q => DDR_DQ_t(i), --[out]
C => Clk, --[in]
D => DQ_oe_cmb, --[in]
S => Rst --[in]
);
end generate DDR_DQ_REG_GEN;
-- If C_INCLUDE_ECC_SUPPORT = 1
-- Include ECC I/O registers
W_DQ_ECC_REG: if C_INCLUDE_ECC_SUPPORT = 1 generate
begin
-------------------------------------------------------------------------------
-- Instantiate the IOB Output registers for ECC data (DQ_ECC_o and DQ_ECC_t)
-------------------------------------------------------------------------------
DDR_DQ_ECC_REG_GEN: for i in 0 to NUM_ECC_BITS-1 generate
attribute IOB : string;
attribute IOB of DDR_DQT_ECC_REG_I : label is "true"; -- only use for FDR components
begin
-- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
-- use ODDR register to generate DQ_ECC_o
DDR_DQ_ECC_REG_V4_I: ODDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT => INIT_0, -- power up low
SRTYPE => SRTYPE_SYNC -- syncronous set & reset
)
port map (
Q => DDR_DQ_ECC_o(i), --[out]
C => Clk, --[in]
CE => Write_data_ecc_en, --[in]
D1 => Write_data_ecc(i), --[in]
D2 => Write_data_ecc(NUM_ECC_BITS+i), --[in]
R => Rst, --[in]
S => '0' --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQT_ECC_REG_I: FDS
port map (
Q => DDR_DQ_ECC_t(i), --[out]
C => Clk, --[in]
D => DQ_ECC_oe_cmb, --[in]
S => Rst --[in]
);
end generate DDR_DQ_ECC_REG_GEN;
end generate W_DQ_ECC_REG;
DDR_DMDQS_REG_GEN: for i in 0 to C_DDR_DWIDTH/8-1 generate
attribute IOB : string;
attribute IOB of DDR_DQST_REG_I : label is "true"; -- only use for FDR components
begin
-- New for Virtex4: ODDR to replace FDDRRSE with IOB attribute
-- use ODDR register to generate DM and DQS
DDR_DM_REG_V4_I: ODDR
generic map (
DDR_CLK_EDGE => DDR_CLK_OPPOSITE_EDGE, -- use clk 180
INIT => INIT_1, -- power up high
SRTYPE => SRTYPE_SYNC -- syncronous set & reset
)
port map (
Q => DDR_DM(i), --[out]
C => Clk, --[in]
CE => Write_data_en, --[in]
D1 => Write_data_mask(i), --[in]
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