📄 io_registers.vhd
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DDR_DQS_ECC_t : out std_logic; -- ECC
DDR_Read_DQS : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_Read_DQS_ECC : out std_logic; -- ECC
DDR_DQS_i : in std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_DQS_o : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_DQS_t : out std_logic_vector(0 to C_DDR_DWIDTH/8-1);
DDR_CSn : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
DDR_RASn : out std_logic;
DDR_CASn : out std_logic;
DDR_WEn : out std_logic;
DDR_BankAddr : out std_logic_vector(0 to C_DDR_BANK_AWIDTH-1);
DDR_Addr : out std_logic_vector(0 to C_DDR_AWIDTH-1);
Clk : in std_logic;
Clk_n : in std_logic;
Clk90 : in std_logic;
Clk90_n : in std_logic;
Clk_ddr_rddata : in std_logic;
Clk_ddr_rddata_n : in std_logic;
Rst : in std_logic
);
end entity io_registers;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of io_registers is
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal ddr_read_data_en_i : std_logic;
signal ddr_read_dqs_ce : std_logic;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- assign output signals
DDR_read_data_en <= ddr_read_data_en_i;
----------------------------------------------------------------------------------
-- For all devices except Virtex4, instantiate DDR registers with IOB attributes
-- Generate statement: if C_FAMILY is not equal to Virtex4 (ie. all other devices)
----------------------------------------------------------------------------------
NOT_VIRTEX4_IOREGS: if not (equalIgnoreCase(C_FAMILY, "virtex4")) generate
-----------------------------------------------------------------------------
-- Attribute declarations
-----------------------------------------------------------------------------
attribute IOB : string;
attribute IOB of DDR_RASN_REG : label is "true";
attribute IOB of DDR_CASN_REG : label is "true";
attribute IOB of DDR_WEN_REG : label is "true";
begin
-------------------------------------------------------------------------------
-- Instantiate the IOB Output registers
-------------------------------------------------------------------------------
DDR_DQ_REG_GEN: for i in 0 to C_DDR_DWIDTH-1 generate
attribute IOB : string;
attribute IOB of DDR_DQ_REG_I : label is "true";
attribute IOB of DDR_DQT_REG_I : label is "true";
begin
-- use DDR register to generate DQ_o
DDR_DQ_REG_I: FDDRRSE
port map (
Q => DDR_DQ_o(i), --[out]
C0 => Clk, --[in]
C1 => clk_n, --[in]
CE => Write_data_en, --[in]
D0 => Write_data(i), --[in]
D1 => Write_data(C_DDR_DWIDTH+i), --[in]
R => Rst, --[in]
S => '0' --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQT_REG_I: FDS
port map (
Q => DDR_DQ_t(i), --[out]
C => Clk, --[in]
D => DQ_oe_cmb, --[in]
S => Rst --[in]
);
end generate DDR_DQ_REG_GEN;
-- If C_INCLUDE_ECC_SUPPORT = 1
-- Include ECC I/O registers
W_DQ_ECC_REG: if C_INCLUDE_ECC_SUPPORT = 1 generate
begin
-------------------------------------------------------------------------------
-- Instantiate the IOB Output registers for ECC data (DQ_ECC_o and DQ_ECC_t)
-------------------------------------------------------------------------------
DDR_DQ_ECC_REG_GEN: for i in 0 to NUM_ECC_BITS-1 generate
attribute IOB : string;
attribute IOB of DDR_DQ_ECC_REG_I : label is "true";
attribute IOB of DDR_DQT_ECC_REG_I : label is "true";
begin
-- use DDR register to generate DQ_ECC_o
DDR_DQ_ECC_REG_I: FDDRRSE
port map (
Q => DDR_DQ_ECC_o(i), --[out]
C0 => Clk, --[in]
C1 => clk_n, --[in]
CE => Write_data_ecc_en, --[in]
D0 => Write_data_ecc(i), --[in]
D1 => Write_data_ecc(NUM_ECC_BITS+i), --[in]
R => Rst, --[in]
S => '0' --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQT_ECC_REG_I: FDS
port map (
Q => DDR_DQ_ECC_t(i), --[out]
C => Clk, --[in]
D => DQ_ECC_oe_cmb, --[in]
S => Rst --[in]
);
end generate DDR_DQ_ECC_REG_GEN;
end generate W_DQ_ECC_REG;
DDR_DMDQS_REG_GEN: for i in 0 to C_DDR_DWIDTH/8-1 generate
attribute IOB : string;
attribute IOB of DDR_DM_REG_I : label is "true";
attribute IOB of DDR_DQST_REG_I : label is "true";
attribute IOB of DDR_DQS_REG_I : label is "true";
begin
-- use DDR register to generate DM and DQS
DDR_DM_REG_I: FDDRRSE
port map (
Q => DDR_DM(i), --[out]
C0 => Clk, --[in]
C1 => clk_n, --[in]
CE => Write_data_en, --[in]
D0 => Write_data_mask(i), --[in]
D1 => Write_data_mask(C_DDR_DWIDTH/8+i), --[in]
R => '0', --[in]
S => Rst --[in]
);
-- DQS is generated from CLK90 so it is centered in the data
-- Assuming pullups are on the board, set DQS based on DQS_setrst
-- and reset based on DQS_rst
DDR_DQS_REG_I: FDDRRSE
port map (
Q => DDR_DQS_o(i), --[out]
C0 => Clk90, --[in]
C1 => clk90_n, --[in]
CE => Write_dqs_en(i), --[in]
D0 => '1', --[in]
D1 => '0', --[in]
R => DQS_rst(i), --[in]
S => DQS_setrst(i) --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQST_REG_I: FDS
port map (
Q => DDR_DQS_t(i), --[out]
C => Clk90, --[in]
D => DQS_oe(i), --[in]
S => '0' --[in]
);
end generate DDR_DMDQS_REG_GEN;
-- If C_INCLUDE_ECC_SUPPORT = 1
-- Include DM_ECC and DQS_ECC I/O registers
W_DQS_ECC_REG: if C_INCLUDE_ECC_SUPPORT = 1 generate
attribute IOB : string;
attribute IOB of DDR_DM_ECC_REG_I : label is "true";
attribute IOB of DDR_DQST_ECC_REG_I : label is "true";
attribute IOB of DDR_DQS_ECC_REG_I : label is "true";
begin
-- use DDR register to generate DM and DQS
DDR_DM_ECC_REG_I: FDDRRSE
port map (
Q => DDR_DM_ECC, --[out]
C0 => Clk, --[in]
C1 => clk_n, --[in]
CE => Write_data_ecc_en, --[in]
D0 => Write_data_ecc_mask(0), --[in]
D1 => Write_data_ecc_mask(1), --[in]
R => '0', --[in]
S => Rst --[in]
);
-- DQS is generated from CLK90 so it is centered in the data
-- Assuming pullups are on the board, set DQS based on DQS_setrst
-- and reset based on DQS_rst
DDR_DQS_ECC_REG_I: FDDRRSE
port map (
Q => DDR_DQS_ECC_o, --[out]
C0 => Clk90, --[in]
C1 => clk90_n, --[in]
CE => Write_dqs_ecc_en, --[in]
D0 => '1', --[in]
D1 => '0', --[in]
R => DQS_ECC_rst, --[in]
S => DQS_ECC_setrst --[in]
);
-- use regular register with io attribute for tri-state control
DDR_DQST_ECC_REG_I: FDS
port map (
Q => DDR_DQS_ECC_t, --[out]
C => Clk90, --[in]
D => DQS_ECC_oe, --[in]
S => '0' --[in]
);
end generate W_DQS_ECC_REG;
-- Can use regular registers with attributes for the rest of the control signals
-- DDR address
DDR_ADDR_REG_GEN: for i in 0 to C_DDR_AWIDTH-1 generate
attribute IOB : string;
attribute IOB of DDR_ADDR_REG_I : label is "true";
begin
DDR_ADDR_REG_I: FDR
port map (
Q => DDR_Addr(i), --[out]
C => Clk, --[in]
D => Addr(i), --[in]
R => Rst --[in]
);
end generate DDR_ADDR_REG_GEN;
-- DDR Bank Address
DDR_BANKADDR_REG_GEN: for i in 0 to C_DDR_BANK_AWIDTH-1 generate
attribute IOB : string;
attribute IOB of DDR_BANKADDR_REG_I : label is "true";
begin
DDR_BANKADDR_REG_I: FDR
port map (
Q => DDR_BankAddr(i), --[out]
C => Clk, --[in]
D => BankAddr(i), --[in]
R => Rst --[in]
);
end generate DDR_BANKADDR_REG_GEN;
-- DDR CSn generate
DDR_CSN_REG_GEN: for i in 0 to C_NUM_BANKS_MEM-1 generate
attribute IOB : string;
attribute IOB of DDR_CSN_REG_I : label is "true";
begin
DDR_CSN_REG_I: FDS
port map (
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