d_ff.vhd

来自「用VHDL语言编写的」· VHDL 代码 · 共 19 行

LIBRARY IEEE;	
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY D_FF IS 
	PORT(A,B:IN STD_LOGIC;	C,D:OUT STD_LOGIC);
END D_FF;
ARCHITECTURE D_FF_ARC OF D_FF IS 
BEGIN
	PROCESS(A,B)
	BEGIN
		IF B'EVENT AND B='1'THEN
		C<=A;	D<=NOT A ;
		END IF ;
	END PROCESS;
END D_FF_ARC;