tasks.v

pci 接口协议 用Verilog编写

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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//                     Lattice Semiconductor Corporation
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// Revision History :
// --------------------------------------------------------------------
//   Ver: | Author            :| Mod. Date :| Changes Made:
//  v1.0 :| D.S.              :| 11/09/98  :| Initial Creation
// --------------------------------------------------------------------
//
//	The cycle generation tasks for pci_stim module inside pci_stim.v  
// 
// --------------------------------------------------------------------


// --------------------------------------------------------------------
// read_config task

task read_config;				

input 	[31:0] address;
input   error_check_en;  // a 1 enables error checking
input   [31:0]  expected_data; // data that should be read back.

begin
    $display($time,"  %m  \t \t  << Reading Config Reg Address = %h >>",address);

    @(posedge pci_clk);                 // address phase
      frame_reg   <= 0;
      frame_oe    <= 1;
      irdy_reg    <= 1;
      irdy_oe     <= 1;
      pci_add_reg <= address;
      pci_add_oe  <= 1;
      pci_cbe_reg <= 4'b1010 ;         // read config command
      pci_cbe_oe  <= 1;
      idsel_reg   <= 1;
 
    @(posedge pci_clk);                 // data phase	
      frame_reg   <= 1;
      frame_oe    <= 1;
      irdy_reg    <= 0;
      irdy_oe     <= 1;
      pci_cbe_reg <= 4'b0000;          // byte enables
      pci_cbe_oe  <= 1;
      idsel_reg   <= 0;
      pci_add_oe  <= 0;
      pci_par_oe  <= 1;
      check_cycle(0, cycle_stat, data_return);      // check cycle termination
        if (error_check_en ) begin 
          check_data(expected_data,data_return);
        end
      irdy_reg    <= 1;
      frame_oe    <= 0;
      irdy_oe     <= 1;
      pci_add_oe  <= 0;
      pci_cbe_oe  <= 0;
    @(posedge pci_clk);                 // end of cycle	
      check_parity;
    $display($time,"  %m  \t \t  << Status = %b >>",cycle_stat);
      frame_oe    <= 0;
      irdy_oe     <= 0;
      pci_par_oe  <= 0;
      kill_time;
    end
    
endtask // of read_config;




// --------------------------------------------------------------------
// write_config task

task write_config;

    input [31:0] address;
    input [31:0] data;

begin
    $display($time,"  %m  \t \t  << Writing Config Reg Address = %h >>",address);

    @(posedge pci_clk);                 // address phase
      frame_reg   <= 0;
      frame_oe    <= 1;
      irdy_reg    <= 1;
      irdy_oe     <= 1;
      pci_add_reg <= address;
      pci_add_oe  <= 1;
      pci_cbe_reg <= 4'b1011;          // write config command
      pci_cbe_oe  <= 1; 
      idsel_reg   <= 1;
 
    @(posedge pci_clk);                 // data phase
      frame_reg   <= 1;
      frame_oe    <= 1;
      irdy_reg    <= 0;
      irdy_oe     <= 1;
      pci_add_reg <= data;
      pci_add_oe  <= 1;
      pci_cbe_reg <= 4'b0000;          // byte enables
      pci_cbe_oe  <= 1;
      idsel_reg   <= 0;
      pci_par_oe  <= 1;
     check_cycle(1, cycle_stat, data_return);      // check cycle termination
 
      irdy_reg    <= 1;
      frame_oe    <= 0;
      irdy_oe     <= 1;
      pci_add_oe  <= 0;
      pci_cbe_oe  <= 0;
      pci_par_oe  <= 1;
 
    @(posedge pci_clk);                 // end of cycle	
      $display($time,"  %m  \t \t  << Status = %b >>",cycle_stat);
      frame_oe    <= 0;
      irdy_oe     <= 0;
      pci_par_oe  <= 0;
      kill_time;
  end
  
endtask



// --------------------------------------------------------------------
// read_cycle task

task read_cycle;

    input [31:0]  address;
    input   error_check_en;  // a 1 enables error checking
    input wait_en; // a 1 enable wait state insertion of long bursts
    input   [31:0]  expected_data; // data that should be read back.
    input	  mode;	              // burst/no burst
    input [3:0]	  brst_size;
    input [2:0] type_signal; // transactin type io or memory
 
    integer	  i;
 
    reg [3:0] type;
begin
    $display($time,"  %m  \t \t  << Reading Address = %h >>",address);
    stop_flag = 0;
    abort_flag = 0;
    type = type_signal;
    @(posedge pci_clk);      
      frame_reg   <= 0;
      frame_oe    <= 1;
      irdy_reg    <= 1;
      irdy_oe     <= 1;
      pci_add_reg <= address;
      pci_add_oe  <= 1;
      pci_cbe_reg <= {type,1'b0};
      pci_cbe_oe  <= 1;
 
    @(posedge pci_clk);
      if (mode  == `no_brst) 
          frame_reg <= 1;
      irdy_reg    <= 0;
      pci_cbe_reg <= 4'b0000;
      frame_oe    <= 1;
      irdy_oe     <= 1;
      pci_add_oe  <= 0;
      pci_cbe_oe  <= 1;
      pci_par_oe  <= 1;	
 
      check_cycle(0, cycle_stat, data_return); 
        if (error_check_en ) begin 
          check_data(expected_data,data_return);
        end
 
      if (mode == `brst && (cycle_stat == `data_tran || cycle_stat == `data_stop))
        begin
	  i = brst_size;
	  while (i)
 	    begin 
	      if (stop_flag == 1 || abort_flag == 1) begin 
	        i = 1;
	      end
	     if (wait_en && i > 5 && i < 7 ) begin 
	       $display($time,"  %m  Master initiating a wait state on read cycle..." );
	       irdy_reg = 1;
	       @(posedge pci_clk);
	       irdy_reg <= 0;
	     end
              if (i == 1)
 	         frame_reg <= 1;
	      @(posedge pci_clk);
	      pci_par_oe <= 0;
	      if (error_check_en) begin 
                expected_data = expected_data + 1;
              end
	      check_cycle(0,cycle_stat, data_return);
              check_parity;
	      if (error_check_en && cycle_stat != `retry_stop) begin 
                check_data(expected_data,data_return);
              end 
              i = i-1;   
	   end
	end
      irdy_reg    <= 1;
      frame_oe    <= 0;
      irdy_oe     <= 1;
      pci_add_oe  <= 0;
      pci_cbe_oe  <= 0;
      pci_par_oe  <= 0;
 
    @(posedge pci_clk);
      check_parity;
      $display($time,"  %m  \t \t  << Status = %b >>",cycle_stat);
      frame_oe    <= 0;
      irdy_oe     <= 0;
      pci_par_oe  <= 0;
      kill_time;
  end
  
endtask //of read_cycle;


// --------------------------------------------------------------------
// write_cycle task

task write_cycle;

    input [31:0]  address; 
    input [31:0]  data;	
    input wait_en; // a one causes a wait state
    input         mode;	// burst or no burst
    input [3:0]	brst_size; // size of burst
    input [2:0] type; // memory or io tran    

    integer	i; 

begin
    $display($time,"  %m  \t \t  << Writing Address = %h >>",address);
    stop_flag = 0;
    abort_flag = 0;

    @(posedge pci_clk);
      frame_reg   <= 0;
      frame_oe    <= 1;
      irdy_reg    <= 1;
      irdy_oe     <= 1;
      pci_add_reg <= address;
      pci_add_oe  <= 1;
      pci_cbe_reg <= {type,1'b1};
      pci_cbe_oe  <= 1;
  
    @(posedge pci_clk);
      if (mode == `no_brst)
           frame_reg <= 1;
      irdy_reg    <= 0;
      pci_add_reg <= data;
      pci_cbe_reg <= 4'b0000;          
      frame_oe    <= 1;
      irdy_oe     <= 1;
      pci_add_oe  <= 1;
      pci_cbe_oe  <= 1;
      pci_par_oe  <= 1;
      check_cycle(1, cycle_stat, data_return);      
      if ((mode == `brst)  && (cycle_stat == `data_tran || cycle_stat == `data_stop))
      begin 
	i = brst_size;
	while (i) begin 
	   pci_add_reg <= pci_add_reg + 1;
	   if (stop_flag == 1 || abort_flag == 1) begin 
	     i = 1;
	   end
	   if (wait_en && i > 5 && i < 7 ) begin 
	     $display($time,"  %m  Master initiating a wait state on a write cycle..." );
	     irdy_reg = 1;
	     @(posedge pci_clk);
	     irdy_reg <= 0;
	   end
	   if (i == 1) 
	     frame_reg <= 1;
	   @(posedge pci_clk);
	   check_cycle(1,cycle_stat, data_return);
	   i = i-1;
	 end
      end

      irdy_reg   <= 1;
      frame_oe   <= 0;
      irdy_oe    <= 1;
      pci_add_oe <= 0;
      pci_cbe_oe <= 0;
      pci_par_oe <= 1;
 
    @(posedge pci_clk);      
      $display($time,"  %m  \t \t  <<  Status = %b >>",cycle_stat);
      frame_oe <= 0;
      irdy_oe <= 0;
      pci_par_oe <= 0;
    
      kill_time;
  end
  
endtask // of write_cycle;