pci_stim.v

pci 接口协议 用Verilog编写

// --------------------------------------------------------------------
// This is the write test. It tests burst and no burst cycles


task write_test;
  begin 
    // run a few burst cycles region 0
    write_cycle(32'h1000_0000, 32'hABCD_0000, `wait_disable, `brst, 4'd5, `io);
    write_cycle(32'h1000_00F0, 32'hFAFA_BABA, `wait_disable, `no_brst, 4'd1, `io);
    // run a few burst cycles region 1
    write_cycle(32'h2000_0000, 32'hCDEF_0000, `wait_enable,`brst, 4'd10, `mem);
    write_cycle(32'h2000_00F0, 32'hBABA_CACA, `wait_disable, `no_brst, 4'd1, `mem);
  end
endtask //of write_test;


// --------------------------------------------------------------------
// This is the write special cycle tests.  It tests retry, stop on a burst
// abort, interupt.

task write_special_cycle;
  begin 
     
    // first test a data retry
    $display($time, "  %m  \t \t  << Initiate a data retry... >>");
    write_cycle(32'h2000_00A0, 32'hAAAA_0000, `wait_disable, `brst, 4'd5, `io);
    if (cycle_stat == `retry_stop) begin 
      $display($time, "  %m  \t \t  << Retry test passed... >>");
    end
    else begin 
      $display($time, "  %m  \t \t  << ERROR: at time %t ps, The Retry Test failed >>",$time);
      num_errors = num_errors + 1;
    end
    
    // next test a data stop from the backend
    $display($time, "  %m  \t \t  << Initiate a data stop on a burt write... >>");
    write_cycle(32'h2000_00B0, 32'hBBBB_0000, `wait_disable,`brst, 4'd10, `io);
    if (cycle_stat == `retry_stop) begin 
      $display($time, "  %m  \t \t  << Data Stop test passed...>>");
    end
    else begin 
      $display($time, "  %m  \t \t  << ERROR: at time %t ps, The Data Stop on a burst write test failed >>",$time);
      num_errors = num_errors + 1;
    end
    
    // next test an abort from the backend
    $display($time,"  %m  \t \t  << Initiate an abort... >>");
    write_cycle(32'h2000_00C0, 32'hCCCC_0000, `wait_disable, `brst, 4'd10, `io);
    if (cycle_stat == `abort) begin 
      $display($time, "  %m  \t \t  << Bkend Abort test passed...>>");
      // read status and command checking for 0C00_0003 
      read_config(32'h0000_0004, 1, 32'h0C00_0003 );
      // set command register bits 1 & 0 & clear the abort
      write_config(32'h0000_0004, 32'h0800_0003); // setup command reg
      // read status and command checking for 0400_0003 abort clear?
      read_config(32'h0000_0004, 1, 32'h0400_0003 );
    end
    else begin 
      $display($time, "  %m  \t \t  << ERROR: at time %t ps, The Bkend Abort test failed>>",$time);
      num_errors = num_errors + 1;
    end
    
    // next test setting and clearing the interupt line
    $display($time,"  %m  \t \t  <<Initiate an interupt...>>");
    interupt_flag = 0;
    write_cycle(32'h2000_00D0, 32'hDDDD_0000, `wait_disable, `no_brst, 4'd1, `io);
    if (pci_inta_l == 0) begin 
      $display($time,"  %m  \t \t  << Disable the interupt...>>");
      write_cycle(32'h2000_00E0, 32'hEEEE_0000, `wait_disable, `no_brst, 4'd1, `io);
      interupt_flag = 1;
    end
    else begin 
      $display($time,"  %m  \t \t  << ERROR: at time %t ps, The Interupt Test failed>>",$time);
      num_errors = num_errors + 1;
      $display($time,"  %m  \t \t  << The pci_inta_l signal was never asserted!!! >>");
    end
    if (interupt_flag == 1 && pci_inta_l !== 1 ) begin 
      $display($time,"  %m  \t \t  << ERROR: at time %t ps, The Interupt Test failed>>",$time);
      num_errors = num_errors + 1;
      $display($time,"  %m  \t \t  << The pci_inta_l signal was never deasserted!!! >>");
    end
    else if (interupt_flag == 1 ) begin
      $display($time,"  %m  \t \t  << The Interupt Test passed...>>");
    end
  end
endtask //of write_special_cycle;



// --------------------------------------------------------------------
// This is the read test. It tests burst and no burst cycles


task read_test;
  begin 
    // run a few burst cycles region 0
    read_cycle(32'h1000_0000, 1, `wait_disable, 32'hABCD_0000, `brst, 4'd5, `io);
    read_cycle(32'h1000_00F0, 1, `wait_disable, 32'hFAFA_BABA, `no_brst, 4'd1, `io);
    // run a few burst cycles region 1
    read_cycle(32'h2000_0000, 1, `wait_enable, 32'hCDEF_0000, `brst, 4'd10, `mem);
    read_cycle(32'h2000_00F0, 1, `wait_disable, 32'hBABA_CACA, `no_brst, 4'd1, `mem);
  end
endtask //of read_test;



// The following test is used to make sure that if the back end device 
// ties data_stop_l low, that even if the master tries to burst,
// it will be forced it to only using single cycles.

task  single_cycle_only_test;
  begin 
  $display($time, "  %m  \t \t  << Starting  single_cycle_only_test >>");  
   data_stop_l = 0; // overides daemon control
                   // forces single cycle transactions
   // even though the following lines say burst 10 only 1 data phase should
   // take place because data_stop_l is 0.
   $display($time, "  %m  \t \t  << Starting  single_cycle_only_test for write>>");
   write_cycle(32'h1000_0000, 32'hFFFF_0000, `wait_enable, `brst, 4'd10,`io);
   $display($time, "  %m  \t \t  << Starting  single_cycle_only_test for read>>");
   read_cycle(32'h1000_0000, 1, `wait_enable, 32'hFFFF_0000, `brst, 4'd10, `io);
 
    if (cycle_stat == `retry_stop) begin 
      $display($time,"  %m  \t \t  << single_cycle_only_test passed...>>");
    end
    else begin 
      $display($time,"  %m  \t \t  << ERROR: at time %t ps, The single_cycle_only_test failed >>",$time);
      num_errors = num_errors + 1;
    end
 
  end
endtask //of single_cycle_only_test




// --------------------------------------------------------------------
// This is the read special cycle test. It tests to make sure the data stop
// on a read works.

task read_special_cycle;
  begin 
     // next test a data stop with a read from the backend
    $display($time,"  %m  \t \t  << Initiate a data stop on a burt read... >>");
    read_cycle(32'h2000_00B0, 1, `wait_disable, 32'hBBBB_0000,`brst, 4'd10, `io);
    if (cycle_stat == `retry_stop) begin 
      $display($time,"  %m  \t \t  << Read Special Cycle test passed...>>");
    end
    else begin 
      $display($time,"  %m  \t \t  << ERROR: at time %t ps, The Data Stop on a burst read test failed >>",$time);
      num_errors = num_errors + 1;
    end  
  
  end
endtask //of read_special_cycle



/**********************************************************************************/
// The following tasks are misc. test bench routines
/**********************************************************************************/

// --------------------------------------------------------------------
// check the cycle termination task

task check_cycle;

    input        write_read;
    output [3:0] cycle_stat;
    output [31:0] data_back; // if readcycle the data returned back
    integer      devsel_cnt;
    integer      trdy_cnt;
 
begin
    devsel_cnt = 0; 
    trdy_cnt   = 0;	                  // wait 4 cycles for devsel 
 
    while(devsel_l && (devsel_cnt < 4) && stop_l) begin  
        @(posedge pci_clk);
        pci_par_oe <= write_read;
        devsel_cnt  = devsel_cnt + 1;
        end
	                                 // wait 16 cycles for trdy
					 // if devsel was active
    while(trdy_l && stop_l && ((trdy_cnt < 16) && (devsel_cnt < 4))) begin
        trdy_cnt = trdy_cnt + 1;
        @(posedge pci_clk);
        pci_par_oe <= write_read;
        end
	
    if ((devsel_cnt < 4) && (trdy_cnt < 16)) begin 
	if (write_read)
	    $display($time," %m  \t \t << Write >>");
 	else
            $display($time," %m  \t \t << Read >>");
 
    case ({trdy_l,stop_l,devsel_l})
	
	   3'b000 : begin 
		cycle_stat  = 4'b0000;
		$display($time,"  %m \t \t << Data Transfered >>");
		$display($time," %m  \t \t  << Bkend requested a stop >>");
		stop_flag = 1;
		 if (!write_read ) begin 
		   data_back = pci_add;
		 end
		end
	
	   3'b001 : begin	
               // this shouldn't happen 
	       cycle_stat  = 4'b0001;	
	       $display($time,"  %m \t \t  <<Data Check Transfer!!!! >>");
	        if (!write_read ) begin 
		  data_back = pci_add;
		end
	       end	
	
	   3'b010 : begin	
	       // normal read or write
	       cycle_stat  = 4'b010;	
	       $display($time,"  %m \t \t  << Data Transfered >>");
	        if (!write_read ) begin 
		  data_back = pci_add;
		end
	       end	
	
	   3'b011 : begin	
               // this shouldn't happen 
	       cycle_stat  = 4'b011;	
	       $display($time,"  %m \t \t << Data Check Transfer!!!! >>");
	        if (!write_read ) begin 
		  data_back = pci_add;
		end
	       end	
	
	   3'b100 : begin	
	       cycle_stat  = 4'b100;	
	       $display($time,"  %m \t \t  << Data Retry or Stop >>");	
	       end	
	
	   3'b101 : begin	
	       cycle_stat  = 4'b101;
	       $display($time,"  %m  \t \t  << Bkend aborting >>");
	       abort_flag = 1;
	       $display($time," %m \t \t  << Data Abort >>");	
	       end	
	
	   3'b110 : begin 
               	// this shouldn't happen	  
	       cycle_stat  = 4'b110;	
	       $display($time,"  %m \t \t << Data Check Transfer!!!! >>");
	       end	
	
	   3'b111 : begin	
	       // this shouldn't happen
	       cycle_stat  = 4'b111;	
	       $display($time,"  %m \t \t << Data Check Transfer >>");	
	       end	
	
	   endcase // if devsel < 4 && trdy_cnt < 16
	
	end
	  
	else if (devsel_cnt == 4 ) begin // changed to 10
 	      cycle_stat    = 4'b1000;
              $display($time,"  %m  \t \t  << No Target Response - Master Abort!!!>>");
              end
        else if (trdy_cnt == 16) begin 
	      cycle_stat = 4'b1001;
              $display($time,"  %m  \t \t  << Target is never ready...Master Abort >>");
              end
end   
endtask // of check_cycle;
	

// --------------------------------------------------------------------
// Task for waiting

task kill_time;
  begin
    @(posedge pci_clk); 
    @(posedge pci_clk);
    @(posedge pci_clk);
    @(posedge pci_clk);
    @(posedge pci_clk);
  end
endtask // of kill_time;

// ---------------------------------------------------------------------
// Tasks for checking return data

task check_data;
  input [31:0] expected, returned;
 
  if (expected !== returned) begin 
    $display($time,"  %m  \t \t  << ERROR: at time %t ps, expected data = %h, received data = %h",$time, expected, returned);
    num_errors = num_errors + 1;
  end
   
endtask //of check_data;



task check_parity;
begin
  if (par_gen !== pci_par) begin 
      $display($time, "  %m  \t \t  << ERROR: Parity Check...parity expected was %b, parity found was %b ", par_gen, pci_par);
      num_errors = num_errors + 1;
  end
end  
endtask //of check_parity



// Include all the cycle generation tasks
// that are part of the pci_stim module
// They are kept in the tasks.v file
// to keep things cleaner. The `include
// basiclly includes the contents of that file
// into this module. Hence giving access to those tasks.
// The path is set for the working directory as the 
// rtl_sim so ../tb_src/tasks.v is the relative path
// to the source file.

 `include "../tb_src/tasks.v"
  
endmodule