pci_clk_reset.v

pci 接口协议 用Verilog编写

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// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// Copyright (c) 2001 by Lattice Semiconductor Corporation
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// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
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// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
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//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
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// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 11/09/98  :| Initial Creation
// --------------------------------------------------------------------
//
//	Module  pci_clk_rest
// This module provides a pci clock output and reset signal.
// Adjust the period and reset_time paramters for whatever  you like.

						
`timescale 1 ns/1 ps		

module pci_clk_reset(
                      pci_clk,
                      reset_l);

// --------------------------------------------------------------------
// port list

output         pci_clk,
               reset_l;

// --------------------------------------------------------------------
// registers

reg            pci_clk,
               reset_l;

// --------------------------------------------------------------------
// parameters

parameter period      = 30;         // pci clock period
parameter reset_time  = 120;	    // reset power-up time

// --------------------------------------------------------------------
// initial assignments

initial begin
        pci_clk <= 1'b0;
	reset_l  <= 1'b0;
	$display($time,": Reset Asserted");
	#reset_time;
	$display($time,": Reset Deasserted");
	reset_l  <= 1'b1;
	end

// --------------------------------------------------------------------
// pci clock generation

always
   #(period/2) pci_clk <= ~pci_clk;

endmodule