📄 pci_tb.v
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// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code for use
// in synthesis for any Lattice programmable logic product. Other
// use of this code, including the selling or duplication of any
// portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice Semiconductor provides no warranty
// regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
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// email: techsupport@latticesemi.com
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// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// v1.0 | D.S. :| 11/02/98 :| birth
// --------------------------------------------------------------------
//
// Module pci_tb
// This is the pci test bench top level. It includes a clock/reset
// module, pci stimulus block, pci target, and backend daemon.
//
`timescale 1ns/100ps
module pci_tb();
// wire declarations
wire pci_clk, reset_l;
wire irdy_l, frame_l, trdy_l, stop_l, devsel_l, pci_par;
wire [31:0] pci_add;
wire [3:0] pci_cbe_l; // t/s not s/t/s
wire idsel;
wire pci_inta_l;
// wire declarations for the backend signals
tri1 [19:0] bkend_ad; // back end address lines; These can be sized.
tri1 [31:0] bkend_dat;
wire [3:0] be_l;
wire base_region0_l, base_region1_l, ready_l;
wire r_w_l, data_write_l;
wire data_stop_l, bkend_int_l, bkend_abort_l;
wire data_read_l;
// signals on the board with pullups require pullups in the testbench.
pullup (irdy_l);
pullup (trdy_l);
pullup (stop_l);
pullup (devsel_l);
pullup (frame_l);
pullup (data_stop_l);
// Instantiation of the clk and reset generator block
pci_clk_reset P_CLK( .pci_clk(pci_clk),
.reset_l(reset_l)
);
// Instantiation of the stimulus generator block
pci_stim STIM( .irdy_l(irdy_l),
.reset_l(reset_l),
.pci_clk(pci_clk),
.frame_l(frame_l),
.trdy_l(trdy_l),
.stop_l(stop_l),
.devsel_l(devsel_l),
.pci_par(pci_par),
.pci_add(pci_add),
.pci_cbe_l(pci_cbe_l),
.idsel(idsel),
.pci_inta_l(pci_inta_l),
.data_stop_l(data_stop_l)
);
bkend_daemon bkend ( .bkend_ad(bkend_ad),
.bkend_dat(bkend_dat),
.be_l(be_l),
.base_region0_l(base_region0_l),
.base_region1_l(base_region1_l),
.ready_l(ready_l),
.r_w_l(r_w_l),
.data_write_l(data_write_l),
.data_read_l(data_read_l),
.data_stop_l(data_stop_l),
.bkend_int_l(bkend_int_l ),
.bkend_abort_l(bkend_abort_l),
.pci_clk(pci_clk),
.pci_rst_l(reset_l)
);
// `ifdefs are used for conditional compiles during simulation
// if the macro GATE is passed at compile time a gate level simulation
// is run, if not by default an RTL simulation is run.
// Gate Level Netlist from Design Direct
`ifdef GATE
// This is the gate level Verilog netlist
// that is simulated if +define+GATE
// is used at verilog compile time
initial
$display("\n << Running an GATE Level simulation DD-CPLD Netlist >> \n");
// instantiation of the gate level verilog netlist
// Use this instantiation ifs your synthesis tool
// keeps the buses in tact.
pci_top CORE( // PCI related signals
.pci_clk(pci_clk),
.pci_rst_l(reset_l),
.pci_irdy_l(irdy_l),
.pci_frame_l(frame_l),
.pci_trdy_l(trdy_l),
.pci_stop_l(stop_l),
.pci_devsel_l(devsel_l),
.pci_par(pci_par),
.pci_ad(pci_add),
.pci_cbe_l(pci_cbe_l),
.pci_idsel(idsel),
.pci_inta_l(pci_inta_l),
// user interface signals
.bkend_ad(bkend_ad),
.bkend_dat(bkend_dat),
.be_l(be_l),
.base_region0_l(base_region0_l),
.base_region1_l(base_region1_l),
.ready_l(ready_l),
.r_w_l(r_w_l),
.data_write_l(data_write_l),
.data_stop_l(data_stop_l),
.data_read_l(data_read_l),
.bkend_int_l(bkend_int_l),
.bkend_abort_l(bkend_abort_l)
);
// Use this instantiation ifs your synthesis tool
// breaks apart the buses
/*
pci_top CORE(
// PCI related signals
.pci_clk(pci_clk),
.pci_rst_l(reset_l),
.pci_irdy_l(irdy_l),
.pci_frame_l(frame_l),
.pci_trdy_l(trdy_l),
.pci_stop_l(stop_l),
.pci_devsel_l(devsel_l),
.pci_par(pci_par),
.pci_idsel(idsel),
.pci_inta_l(pci_inta_l),
.pci_ad_31(pci_add[31]),
.pci_ad_30(pci_add[30]),
.pci_ad_29(pci_add[29]),
.pci_ad_28(pci_add[28]),
.pci_ad_27(pci_add[27]),
.pci_ad_26(pci_add[26]),
.pci_ad_25(pci_add[25]),
.pci_ad_24(pci_add[24]),
.pci_ad_23(pci_add[23]),
.pci_ad_22(pci_add[22]),
.pci_ad_21(pci_add[21]),
.pci_ad_20(pci_add[20]),
.pci_ad_19(pci_add[19]),
.pci_ad_18(pci_add[18]),
.pci_ad_17(pci_add[17]),
.pci_ad_16(pci_add[16]),
.pci_ad_15(pci_add[15]),
.pci_ad_14(pci_add[14]),
.pci_ad_13(pci_add[13]),
.pci_ad_12(pci_add[12]),
.pci_ad_11(pci_add[11]),
.pci_ad_10(pci_add[10]),
.pci_ad_9(pci_add[9]),
.pci_ad_8(pci_add[8]),
.pci_ad_7(pci_add[7]),
.pci_ad_6(pci_add[6]),
.pci_ad_5(pci_add[5]),
.pci_ad_4(pci_add[4]),
.pci_ad_3(pci_add[3]),
.pci_ad_2(pci_add[2]),
.pci_ad_1(pci_add[1]),
.pci_ad_0(pci_add[0]),
.pci_cbe_l_3(pci_cbe_l[3]),
.pci_cbe_l_2(pci_cbe_l[2]),
.pci_cbe_l_1(pci_cbe_l[1]),
.pci_cbe_l_0(pci_cbe_l[0]),
// user interface signals
.bkend_ad_19(bkend_ad[19]),
.bkend_ad_18(bkend_ad[18]),
.bkend_ad_17(bkend_ad[17]),
.bkend_ad_16(bkend_ad[16]),
.bkend_ad_15(bkend_ad[15]),
.bkend_ad_14(bkend_ad[14]),
.bkend_ad_13(bkend_ad[13]),
.bkend_ad_12(bkend_ad[12]),
.bkend_ad_11(bkend_ad[11]),
.bkend_ad_10(bkend_ad[10]),
.bkend_ad_9(bkend_ad[9]),
.bkend_ad_8(bkend_ad[8]),
.bkend_ad_7(bkend_ad[7]),
.bkend_ad_6(bkend_ad[6]),
.bkend_ad_5(bkend_ad[5]),
.bkend_ad_4(bkend_ad[4]),
.bkend_ad_3(bkend_ad[3]),
.bkend_ad_2(bkend_ad[2]),
.bkend_ad_1(bkend_ad[1]),
.bkend_ad_0(bkend_ad[0]),
.bkend_dat_31(bkend_dat[31]),
.bkend_dat_30(bkend_dat[30]),
.bkend_dat_29(bkend_dat[29]),
.bkend_dat_28(bkend_dat[28]),
.bkend_dat_27(bkend_dat[27]),
.bkend_dat_26(bkend_dat[26]),
.bkend_dat_25(bkend_dat[25]),
.bkend_dat_24(bkend_dat[24]),
.bkend_dat_23(bkend_dat[23]),
.bkend_dat_22(bkend_dat[22]),
.bkend_dat_21(bkend_dat[21]),
.bkend_dat_20(bkend_dat[20]),
.bkend_dat_19(bkend_dat[19]),
.bkend_dat_18(bkend_dat[18]),
.bkend_dat_17(bkend_dat[17]),
.bkend_dat_16(bkend_dat[16]),
.bkend_dat_15(bkend_dat[15]),
.bkend_dat_14(bkend_dat[14]),
.bkend_dat_13(bkend_dat[13]),
.bkend_dat_12(bkend_dat[12]),
.bkend_dat_11(bkend_dat[11]),
.bkend_dat_10(bkend_dat[10]),
.bkend_dat_9(bkend_dat[9]),
.bkend_dat_8(bkend_dat[8]),
.bkend_dat_7(bkend_dat[7]),
.bkend_dat_6(bkend_dat[6]),
.bkend_dat_5(bkend_dat[5]),
.bkend_dat_4(bkend_dat[4]),
.bkend_dat_3(bkend_dat[3]),
.bkend_dat_2(bkend_dat[2]),
.bkend_dat_1(bkend_dat[1]),
.bkend_dat_0(bkend_dat[0]),
.be_l_3(be_l[3]),
.be_l_2(be_l[2]),
.be_l_1(be_l[1]),
.be_l_0(be_l[0]),
.base_region0_l(base_region0_l),
.base_region1_l(base_region1_l),
.ready_l(ready_l),
.r_w_l(r_w_l),
.data_write_l(data_write_l),
.data_stop_l(data_stop_l),
.data_read_l(data_read_l),
.bkend_int_l(bkend_int_l),
.bkend_abort_l(bkend_abort_l)
);
*/
/* This is taken care of in the script now.
initial
begin
$sdf_annotate("./gate/pci_top.sdf", pci_tb.CORE);
end
*/
`else
// RTL version of the design, it is simulated
// if +define+GATE is NOT used at verilog compile
// time.
initial
$display("\n << Running an RTL simulation >> \n");
// Instantiation of the PCI Target Reference Design
pci_top CORE( // PCI related signals
.pci_clk(pci_clk),
.pci_rst_l(reset_l),
.pci_irdy_l(irdy_l),
.pci_frame_l(frame_l),
.pci_trdy_l(trdy_l),
.pci_stop_l(stop_l),
.pci_devsel_l(devsel_l),
.pci_par(pci_par),
.pci_ad(pci_add),
.pci_cbe_l(pci_cbe_l),
.pci_idsel(idsel),
.pci_inta_l(pci_inta_l),
// user interface signals
.bkend_ad(bkend_ad),
.bkend_dat(bkend_dat),
.be_l(be_l),
.base_region0_l(base_region0_l),
.base_region1_l(base_region1_l),
.ready_l(ready_l),
.r_w_l(r_w_l),
.data_write_l(data_write_l),
.data_stop_l(data_stop_l),
.data_read_l(data_read_l),
.bkend_int_l(bkend_int_l),
.bkend_abort_l(bkend_abort_l)
);
`endif
endmodule
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