fifo_sync.vhd

脉冲同步电路,简单修改就可以使用,很使用的.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fifo_sync is
    Port ( CLK : in std_logic;
           SIN : in std_logic;
           SOUT : out std_logic;
           DIR : in std_logic);	--dir='1',当检测到SIN有下降沿时,SOUT输出一个正脉冲同步于CLK的下降沿,脉宽是1个clk
end fifo_sync;								--dir='0',当检测到SIN有上升沿时,SOUT输出一个正脉冲同步于CLK的下降沿,脉宽是1个clk

architecture Behavioral of fifo_sync is
signal s0,s1,s2 : std_logic;
signal sig : std_logic;
begin

sig <= sin when DIR = '0' else not sin;

process(CLK)
begin
if CLK'event and CLK = '1' then
  s0 <= sig;
  s2 <= s1;
end if;
end process;
-----------------
process(CLK)
begin
if CLK'event and CLK = '0' then
  s1 <= s0;
end if;
end process;

SOUT <= (not s2) and s0;

end Behavioral;