seg_decode.vhd

DE2平台键控传输

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY seg_decode IS
       PORT(b1,b2,b3,b4,b5,b6,b7,b8   : IN  std_logic;
            a,b,c,d,e,f,g             : OUT std_logic     
            );
END seg_decode;

ARCHITECTURE seg_decode_arch OF seg_decode IS
     SIGNAL data_tmp : std_logic_vector (6 DOWNTO 0);
BEGIN
  PROCESS(b1,b2,b3,b4,b5,b6,b7,b8)
     VARIABLE seg : std_logic_vector(7 DOWNTO 0);
  BEGIN  
     seg := b8&b7&b6&b5&b4&b3&b2&b1;
     CASE seg IS
          WHEN "01000101" => data_tmp <="1000000";
          WHEN "00011010" => data_tmp <="1111001";
          WHEN "00011110" => data_tmp <="0100100";
          WHEN "00100110" => data_tmp <="0110000";
          WHEN "00100101" => data_tmp <="0011001";
          WHEN "00101110" => data_tmp <="0010010";
          WHEN "00110110" => data_tmp <="0000010";
          WHEN "00111101" => data_tmp <="1011000";
          WHEN "00111110" => data_tmp <="0000000";
          WHEN "01000110" => data_tmp <="0010000";
          WHEN OTHERS     => data_tmp <="1111111";
     END CASE;
  END PROCESS;
  a <= data_tmp(0);
  b <= data_tmp(1);
  c <= data_tmp(2);
  d <= data_tmp(3);
  e <= data_tmp(4);
  f <= data_tmp(5);
  g <= data_tmp(6);
END seg_decode_arch;