contr.vhd

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contr is
port(clk,clk1,clk2,clk3,pause,sel,set:in std_logic;
     clkh,clkm,clks,clkmm:buffer std_logic;
      s0,s1,s2,s3,s4,s5:out std_logic);
end;
architecture d of contr is
signal tem:std_logic_vector(2 downto 0);
begin
process(sel)
begin
if sel'event and sel='0' then
  if tem="110" then
    tem<="000";
  else tem<=tem+'1';
  end if;
end if;
end process;


process(pause,tem,set)
begin
if pause='0' then
	clkh<=clkh;
	clkm<=clkm;
	clks<=clks;
	clkmm<=clkmm;
 else
   case tem is
			when"000"=>clkh<=clk3;clkm<=clk2;clks<=clk1;clkmm<=clk;
						s0<='1';s1<='1';s2<='1';s3<='1';s4<='1';s5<='1';
			when"001"=>clkh<=clkh;clkm<=clkm;clks<=set;clkmm<=clkmm;
						s0<='1';s1<='1';s2<='1';s3<='1';s4<='1';s5<='0';
			when"010"=>clkh<=clkh;clkm<=clkm;clks<=set;clkmm<=clkmm;
						s0<='1';s1<='1';s2<='1';s3<='1';s4<='0';s5<='1';
			when"011"=>clkh<=clkh;clkm<=set;clks<=clks;clkmm<=clkmm;
						s0<='1';s1<='1';s2<='1';s3<='0';s4<='1';s5<='1';
			when"100"=>clkh<=clkh;clkm<=set;clks<=clks;clkmm<=clkmm;
						s0<='1';s1<='1';s2<='0';s3<='1';s4<='1';s5<='1';
			when"101"=>clkh<=set;clkm<=clkm;clks<=clks;clkmm<=clkmm;
						s0<='1';s1<='0';s2<='1';s3<='1';s4<='1';s5<='1';
			when"110"=>clkh<=set;clkm<=clkm;clks<=clks;clkmm<=clkmm;
						s0<='0';s1<='1';s2<='1';s3<='1';s4<='1';s5<='1';
			when others=>null;
	end case;
end if;
end process;
end;