sec.vhd

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sec is
port(clk,clr,set0,set1:in std_logic;
     co:buffer std_logic;
     ge,shi:buffer std_logic_vector(3 downto 0));
end;
architecture sec_1 of sec is
begin 
process(clk,clr)
begin
if clr='0' then
	ge<="0000";
	shi<="0000";
  elsif clk'event and clk='0' then 

  if set1='0' then
    if shi="1001" then
       shi<="0000";
     else shi<=shi+'1';
    end if;
  elsif set0='0' then
    if ge="1001" then
       ge<="0000";
     else ge<=ge+'1';
    end if;

  
  elsif ge="1001" and shi="0101" then
     co<=not co;
     ge<="0000";
	 shi<="0000";
    elsif ge="1001" and shi="0010" then
      co<=not co;
      ge<="0000";
       shi<=shi +'1';
      elsif ge="1001" then
        shi<=shi +'1';
        ge<="0000";
      else ge<=ge+'1';
  end if;
   
end if;
end process;
end;