state1.msg

来自「Design and Test_Verilog HDL——EDA先锋工作室《设计」· MSG 代码 · 共 14 行

@TM:1134715757
@W: BN132 :"":0:0:0:-1|Removing instance o2_22_u,  because it is equivalent to instance N_79_i
@W: BN132 :"":0:0:0:-1|Removing instance o1_23_u,  because it is equivalent to instance N_6_i
@TM:1134715517
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1134715515
@N:  :"c:\prj\fsm_abc\state1\state1.v":6:7:6:12|Synthesizing module state1
@TM:1134715517
@W: BN132 :"c:\prj\fsm_abc\state1\state1.v":27:0:27:5|M
@TM:1134715515
@N: CL201 :"c:\prj\fsm_abc\state1\state1.v":27:0:27:5|M