state2.srs

Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Dec 16 18:27:34 2005
#
#
#OPTIONS:"|-fixsmult|-dspmac|-nram|-divnmod|-I|C:\\prj\\Example-6-1\\FSM\\state2\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\stratix.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v|-autosm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\stratix.v":1092904038
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\stratix.v":1092904038
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v":1092812196
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v":1092812196
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v":1111562108
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v":1111562108
#CUR:"C:\\prj\\Example-6-1\\FSM\\state2\\state2.v":1134714582
#CUR:"C:\\prj\\Example-6-1\\FSM\\state2\\state2.v":1134714582
f "C:\eda\synplicity\fpga_81\lib\altera\altera.v"; # file 0
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\stratix.v"; # file 1
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; # file 2
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v"; # file 3
af .is_verilog 1;
f "C:\prj\Example-6-1\FSM\state2\state2.v"; # file 4
af .is_verilog 1;
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