traffic_lamp.vhd

a program about traffic light demo.

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-- Company: 
-- Engineer:
--
-- Create Date:    10:57:25 11/30/07
-- Design Name:    
-- Module Name:    traffic_lamp - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity traffic_lamp is
    Port ( clk : in std_logic;
           s : in std_logic;
			  rst: in std_logic;
           r1 : out std_logic;
           r2 : out std_logic;
           y1 : out std_logic;
           y2 : out std_logic;
           g1 : out std_logic;
           g2 : out std_logic);
end traffic_lamp;

architecture Behavioral of traffic_lamp is
	constant timeMax: integer :=60; --60s
	constant timeRG:  integer :=20; --20s
	constant timeRY:  integer :=4;  --4s
	constant timeGR:  integer :=60; --60s
	constant timeYR:  integer :=4;  --4s
	constant timeTest:integer :=1;  --1s
	type state is(RG,RY,GR,YR);
	signal pr_state, nx_state: state;
	signal time: integer range 0 to timeMax;
begin
	-------------------------Lower Section of state macine---------------------
	process(clk,stby)
		variable count: integer range 0 to timeMax;
	begin
		if(rst='1')then
			pr_state<=GR;
			count:=0;
		elsif(clk'event and clk='1') then
			count:=count+1;
			if(count=time) then
				pr_state<=nx_state;
				count:=0;
			end if;
		end if;
	end process;
	-------------------------Upper section of state machine--------------------
	process(pr_state,test)
	begin
		case pr_state is
			when RG =>
				r1<='1';r2<='0';y1<='0';y2<='0';g1<='0';g2<='1';
				nx_state<=RY;
				if(test='0') then time<=timeRG;
				else time<=timeTest;
				end if;
			when RY =>
				r1<='1';r2<='0';y1<='0';y2<='1';g1<='0';g2<='0';
				nx_state<=GR;
				if(test='0') then time<=timeRY;
				else time<=timeTest;
				end if;
			when GR =>
				r1<='0';r2<='1';y1<='0';y2<='0';g1<='1';g2<='0';
				nx_state<=YR;
				if(test='0') then time<=timeGR;
				else time<=timeTest;
				end if;
			when YR =>
				r1<='0';r2<='1';y1<='1';y2<='0';g1<='0';g2<='0';
				nx_state<=RG;
				if(test='0') then time<=timeYR;
				else time<=timeTest;
				end if;
--			when YY =>
--				r1<='0';r2<='0';y1<='1';y2<='1';g1<='0';g2<='0';
--				nx_state<=RY;
		end case;
	end process;
end Behavioral;