bk_shift0

用Verilog实现国内第一个商用密码算法SMS4的加密和解密。

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module B_SHIFT0 (b0_out,
                 b0_in,
                 clk,
                 reset);
                 
parameter BWIDTH=32;

output [BWIDTH-1:0] b0_out;
reg    [BWIDTH-1:0] b0_out;
input  [BWIDTH-1:0] b0_in;
reg    [BWIDTH-1:0] b0_out_wire;
input  clk;
input  reset;

always @ (posedge clk or negedge reset)
  if (!reset)
    b0_out<=0;
      else
        b0_out<=b0_out_wire;
             
always @ (b0_in)
    b0_out_wire=b0_in;
endmodule