b_shift0.v

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· Verilog 代码 · 共 19 行

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module B_SHIFT0 (b0_out,
                 b0_in
                 );
                 
parameter BWIDTH=32;

output [0:BWIDTH-1] b0_out;
reg    [0:BWIDTH-1] b0_out;
input  [0:BWIDTH-1] b0_in;


always @ (b0_in)
    b0_out=b0_in;
endmodule