bk_shift2

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· 代码 · 共 60 行

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module B_SHIFT2 (b2_out,
                  b2_in,
                  clk,
                  reset);

parameter BWIDTH=32;

output [BWIDTH-1:0] b2_out;
reg    [BWIDTH-1:0] b2_out;
input  [BWIDTH-1:0] b2_in;
reg    [BWIDTH-1:0] b2_out_wire;
input  clk;
input  reset;

always @ (posedge clk or negedge reset)
   if (!reset)
      b2_out<=0;
       else
         b2_out<=b2_out_wire;       
         
always @ (b2_in)
   begin : shift
     b2_out_wire[31]=b2_in[8];
     b2_out_wire[30]=b2_in[7];
     b2_out_wire[29]=b2_in[6];
     b2_out_wire[28]=b2_in[5];
     b2_out_wire[27]=b2_in[4];
     b2_out_wire[26]=b2_in[3];
     b2_out_wire[25]=b2_in[2];
     b2_out_wire[24]=b2_in[1];
     b2_out_wire[23]=b2_in[0];
     b2_out_wire[22]=b2_in[31];
     b2_out_wire[21]=b2_in[30];
     b2_out_wire[20]=b2_in[29];
     b2_out_wire[19]=b2_in[28];
     b2_out_wire[18]=b2_in[27];
     b2_out_wire[17]=b2_in[26];
     b2_out_wire[16]=b2_in[25];
     b2_out_wire[15]=b2_in[24];
     b2_out_wire[14]=b2_in[23];
     b2_out_wire[13]=b2_in[22];
     b2_out_wire[12]=b2_in[21];
     b2_out_wire[11]=b2_in[20];
     b2_out_wire[10]=b2_in[19];
     b2_out_wire[9]=b2_in[18];
     b2_out_wire[8]=b2_in[17];
     b2_out_wire[7]=b2_in[16];
     b2_out_wire[6]=b2_in[15];
     b2_out_wire[5]=b2_in[14];
     b2_out_wire[4]=b2_in[13];
     b2_out_wire[3]=b2_in[12];
     b2_out_wire[2]=b2_in[11];
     b2_out_wire[1]=b2_in[10];
     b2_out_wire[0]=b2_in[9]; 
   end 
endmodule