edcrypt_ori_test.v

用Verilog实现国内第一个商用密码算法SMS4的加密和解密。

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on

module edcrypt_ori_test;

reg  [0:127] data_in;
reg  [0:31]  round_key;
reg  get_data;
reg  ed_run;
reg  [0:4] counter;
reg  mode;
reg  clk;
reg  reset;

wire [0:127] data_out;

edcrypt  edcrypt_test(
                      .data_out(data_out),
                      .data_in(data_in),
                      .round_key(round_key),
                      .get_data(get_data),
                      .ed_run(ed_run),
                      .counter(counter),
                      .mode(mode),
                      .clk(clk),
                      .reset(reset)
                      );

                      
initial
 begin
  data_in=128'b11110100000000000111101011101000111000101100101001001110110001010010111001011000010010010101110011011110100011100010100010111101;
  round_key=32'b11111101100101010000000000111100;
  counter=5'b10101;
  reset=0;
  clk=0;
  $display ("the input data is : %h", data_in);
  $display ("the input round_key is : %h", round_key);
  #5
  get_data=1;
  #5
  reset=1;
  #5
  get_data=0;
  ed_run=1;
  mode=1;
  #300
  $display ("the output data is : %h", data_out);
  $stop;
  end
  
always #2 clk=~clk;


endmodule