ck.v.bak

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· BAK 代码 · 共 44 行

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module CK (ck,
           counter);

output [0:31] ck;
input  [0:4] counter;

reg    [0:31] ck;
reg    [0:6] cou_3,cou_2,cou_1,cou_0;
reg    [0:9] ck_3,ck_2,ck_1,ck_0;
reg    [0:7] mod_3,mod_2,mod_1,mod_0;

always @ (counter)
  begin
    cou_3={counter,2'b0};
    cou_2=cou_3;
    cou_1=cou_3;
    cou_0=cou_3;
  end

always @ (cou_3 or cou_2 or cou_1 or cou_0)
  begin
    ck_3=({(cou_3+3),3'b0})-(cou_3+3);
    ck_2=({(cou_3+2),3'b0})-(cou_3+2);
    ck_1=({(cou_3+1),3'b0})-(cou_3+1);
    ck_0=({(cou_3+0),3'b0})-(cou_3+0);
  end
  
always @ (ck_3 or ck_2 or ck_1 or ck_0)
  begin
    mod_3=ck_3[7:0];
    mod_2=ck_2[7:0];
    mod_1=ck_1[7:0];
    mod_0=ck_0[7:0];
  end
  
always @ (mod_3 or mod_2 or mod_1 or mod_0)
  ck={mod_0,mod_1,mod_2,mod_3};

endmodule