_primary.vhd

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity key_expand_ori is
    generic(
        dwidth           : integer := 128;
        rwidth           : integer := 32;
        fk1              : integer := 1453994832;
        fk2              : integer := 1736282519
    );
    port(
        key_out         : out    vl_logic_vector;
        round_key       : out    vl_logic_vector;
        key_in          : in     vl_logic_vector;
        get_key         : in     vl_logic;
        exp_run         : in     vl_logic;
        mode            : in     vl_logic;
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        counter         : in     vl_logic_vector(0 to 4)
    );
end key_expand_ori;