_primary.vhd

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· VHDL 代码 · 共 39 行

library verilog;
use verilog.vl_types.all;
entity sms4_control_ori is
    generic(
        dwidth           : integer := 128;
        idle             : integer := 0;
        getkey1          : integer := 1;
        getkey2          : integer := 2;
        keyexp           : integer := 3;
        waitdata         : integer := 4;
        getdatask1       : integer := 5;
        getdatask2       : integer := 6;
        round1a          : integer := 7;
        round1b          : integer := 8;
        round2a          : integer := 10;
        finish1          : integer := 11;
        waitnext         : integer := 12;
        wait_clk         : integer := 13;
        finish2          : integer := 14
    );
    port(
        busy            : out    vl_logic;
        dout_vld        : out    vl_logic;
        key_str         : out    vl_logic;
        get_data        : out    vl_logic;
        get_key         : out    vl_logic;
        counter         : out    vl_logic_vector(0 to 4);
        mode            : out    vl_logic;
        exp_run         : out    vl_logic;
        ed_run          : out    vl_logic;
        start           : in     vl_logic;
        enc             : in     vl_logic;
        din_vld         : in     vl_logic;
        key_vld         : in     vl_logic_vector(0 to 1);
        clk             : in     vl_logic;
        reset           : in     vl_logic
    );
end sms4_control_ori;