_primary.vhd

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity edcrypt_ori is
    generic(
        dwidth           : integer := 128;
        rwidth           : integer := 32
    );
    port(
        data_out        : out    vl_logic_vector;
        data_in         : in     vl_logic_vector;
        round_key       : in     vl_logic_vector;
        get_data        : in     vl_logic;
        ed_run          : in     vl_logic;
        clk             : in     vl_logic;
        reset           : in     vl_logic
    );
end edcrypt_ori;