bk_shift1.v.bak

用Verilog实现国内第一个商用密码算法SMS4的加密和解密。

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module BK_SHIFT1 (b1_out,
                  b1_in
                  );

parameter BWIDTH=32;

output [0:BWIDTH-1] b1_out;
reg    [0:BWIDTH-1] b1_out;
input  [0:BWIDTH-1] b1_in;

always @ (b1_in)
   begin : shift
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[];
     b1_out[]=b1_in[]; 
   end 
endmodule