yunsuan22.hif

vhd语言

HIF003
--
-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	f74163.gdf
	{
		f74163 [] []
		{
			20 [] [];
		}
	}
	altram.tdf
	{
		altram [DEVICE_FAMILY,USE_EAB=ON,REGISTERINPUTMODE=DEFAULT,FILE=NO_FILE,NUMWORDS,AD_WIDTH,WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [memmodes.inc,lpm_decode.inc,lpm_mux.inc,aglobal.inc]
		{
			15 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE=NO_FILE,NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
		}
	}
	f74161.gdf
	{
		f74161 [] []
		{
			12 [] [];
		}
	}
	4sel1.gdf
	{
		4sel1 [] []
		{
			7 [] [];
		}
	}
	2sel1.gdf
	{
		2sel1 [] []
		{
			6 [] [];
		}
	}
	74163.tdf
	{
		74163 [DEVICE_FAMILY,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
		{
			19 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [LDN,CLRN,CLK,ENP,RCO,ENT,D,C,B,QD,QC,QB,QA,A];
		}
	}
	cdu16.gdf
	{
		cdu16 [] []
		{
			18 [] [];
		}
	}
	lpm_ram_io.tdf
	{
		lpm_ram_io [DEVICE_FAMILY,LPM_FILE=NO_FILE,LPM_OUTDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS,LPM_WIDTHAD,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [altram.inc,lpm_mux.inc,lpm_decode.inc,aglobal.inc]
		{
			14 [DEVICE_FAMILY=FLEX10K,LPM_FILE=NO_FILE,LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
		}
	}
	74161.tdf
	{
		74161 [DEVICE_FAMILY,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
		{
			13 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [ENP,CLK,CLRN,B,C,D,ENT,QA,QB,QC,QD,A,LDN];
			11 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [ENP,CLK,CLRN,RCO,B,C,D,ENT,QA,QB,QC,QD,A,LDN];
		}
	}
	74257.gdf
	{
		74257 [] []
		{
			10 [] [];
		}
	}
	multi.vhd
	{
		ONE_BIT_ADDER [] []
		{
			9 [] [];
		}
		multi [] [U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			8 [] [];
		}
	}
	risel.gdf
	{
		risel [] []
		{
			5 [] [];
		}
	}
	cdu.gdf
	{
		cdu [] []
		{
			17 [] [];
		}
	}
	74181.gdf
	{
		74181 [] []
		{
			4 [] [];
		}
	}
	74273.gdf
	{
		74273 [] []
		{
			3 [] [];
		}
	}
	74374.gdf
	{
		74374 [] []
		{
			2 [] [];
		}
	}
	74244.gdf
	{
		74244 [] []
		{
			1 [] [];
		}
	}
	74373.gdf
	{
		74373 [] []
		{
			16 [] [];
		}
	}
	yunsuan22.gdf
	{
		yunsuan22 [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	yunsuan22::(0,0):(0): yunsuan22.gdf
	{
		74257::(0,0):(159): 74257.gdf;
		74257::(0,0):(160): 74257.gdf;
		multi::(0,0):(161): multi.vhd
		{
			one_bit_adder:9:(104,9):(2382,U_4_5): multi.vhd;
			one_bit_adder:9:(103,9):(2381,U_4_4): multi.vhd;
			one_bit_adder:9:(102,9):(2380,U_4_3): multi.vhd;
			one_bit_adder:9:(101,9):(2379,U_4_2): multi.vhd;
			one_bit_adder:9:(100,9):(2378,U_4_1): multi.vhd;
			one_bit_adder:9:(99,9):(2377,U_4_0): multi.vhd;
			one_bit_adder:9:(97,9):(2376,U_3_5): multi.vhd;
			one_bit_adder:9:(96,9):(2375,U_3_4): multi.vhd;
			one_bit_adder:9:(95,9):(2374,U_3_3): multi.vhd;
			one_bit_adder:9:(94,9):(2373,U_3_2): multi.vhd;
			one_bit_adder:9:(93,9):(2372,U_3_1): multi.vhd;
			one_bit_adder:9:(92,9):(2371,U_3_0): multi.vhd;
			one_bit_adder:9:(90,9):(2370,U_2_5): multi.vhd;
			one_bit_adder:9:(89,9):(2369,U_2_4): multi.vhd;
			one_bit_adder:9:(88,9):(2368,U_2_3): multi.vhd;
			one_bit_adder:9:(87,9):(2367,U_2_2): multi.vhd;
			one_bit_adder:9:(86,9):(2366,U_2_1): multi.vhd;
			one_bit_adder:9:(85,9):(2365,U_2_0): multi.vhd;
			one_bit_adder:9:(83,9):(2364,U_1_5): multi.vhd;
			one_bit_adder:9:(82,9):(2363,U_1_4): multi.vhd;
			one_bit_adder:9:(81,9):(2362,U_1_3): multi.vhd;
			one_bit_adder:9:(80,9):(2361,U_1_2): multi.vhd;
			one_bit_adder:9:(79,9):(2360,U_1_1): multi.vhd;
			one_bit_adder:9:(78,9):(2359,U_1_0): multi.vhd;
			one_bit_adder:9:(76,9):(2358,U_0_5): multi.vhd;
			one_bit_adder:9:(75,9):(2357,U_0_4): multi.vhd;
			one_bit_adder:9:(74,9):(2356,U_0_3): multi.vhd;
			one_bit_adder:9:(73,9):(2355,U_0_2): multi.vhd;
			one_bit_adder:9:(72,9):(2354,U_0_1): multi.vhd;
			one_bit_adder:9:(71,9):(2353,U_0_0): multi.vhd;
		}
		74181::(0,0):(174): 74181.gdf;
		74181::(0,0):(175): 74181.gdf;
		74273::(0,0):(176): 74273.gdf;
		74273::(0,0):(177): 74273.gdf;
		74374::(0,0):(178): 74374.gdf;
		74374::(0,0):(179): 74374.gdf;
		74374::(0,0):(180): 74374.gdf;
		74374::(0,0):(181): 74374.gdf;
		74244::(0,0):(182): 74244.gdf;
		74244::(0,0):(183): 74244.gdf;
		74244::(0,0):(184): 74244.gdf;
		lpm_ram_io::(0,0):(92): lpm_ram_io.tdf
		{
			altram:15:(66,5):(48,sram): altram.tdf;
		}
		74161::(0,0):(79): 74161.tdf
		{
			f74161:12:(33,3):(41,sub): f74161.gdf;
		}
		74161::(0,0):(78): 74161.tdf
		{
			f74161:12:(33,3):(41,sub): f74161.gdf;
		}
		74273::(0,0):(83): 74273.gdf;
		74244::(0,0):(82): 74244.gdf;
		74373::(0,0):(97): 74373.gdf;
		risel::(0,0):(186): risel.gdf
		{
			4sel1:7:(0,0):(12): 4sel1.gdf;
			2sel1:6:(0,0):(17): 2sel1.gdf;
		}
	}
}