bcd7.rpt
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RPT
570 行
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zhuhui\mycpu\xianshi\bcd7.rpt
bcd7
** EQUATIONS **
IN0 : INPUT;
IN1 : INPUT;
IN2 : INPUT;
IN3 : INPUT;
-- Node name is 'A' from file "bcd7.tdf" line 25, column 9
-- Equation name is 'A', location is LC1_B3, type is buried.
A = LCELL( _EQ001);
_EQ001 = IN0 & IN2 & !IN3
# !IN0 & IN3
# IN1 & !IN3
# !IN0 & !IN2
# !IN1 & !IN2 & IN3
# IN0 & IN1 & IN2;
-- Node name is 'B' from file "bcd7.tdf" line 23, column 11
-- Equation name is 'B', location is LC2_B3, type is buried.
B = LCELL( _EQ002);
_EQ002 = IN0 & IN1 & !IN3
# !IN2 & !IN3
# IN0 & !IN1 & IN3
# !IN0 & !IN2
# !IN1 & !IN2
# !IN0 & !IN1 & !IN3;
-- Node name is 'B~1' from file "bcd7.tdf" line 23, column 11
-- Equation name is 'B~1', location is LC5_B3, type is buried.
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ003);
_EQ003 = IN0 & IN1 & IN2 & !IN3
# IN0 & !IN1 & !IN2 & !IN3;
-- Node name is 'C' from file "bcd7.tdf" line 23, column 13
-- Equation name is 'C', location is LC4_B3, type is buried.
C = LCELL( _EQ004);
_EQ004 = !_LC3_B3
# _LC5_B3
# _LC6_B3
# _LC7_B3;
-- Node name is 'C~1' from file "bcd7.tdf" line 23, column 13
-- Equation name is 'C~1', location is LC7_B3, type is buried.
-- synthesized logic cell
_LC7_B3 = LCELL( _EQ005);
_EQ005 = !IN2 & IN3
# !IN1 & IN2 & !IN3
# !IN0 & IN2 & !IN3;
-- Node name is 'D' from file "bcd7.tdf" line 24, column 15
-- Equation name is 'D', location is LC7_A24, type is buried.
D = LCELL( _EQ006);
_EQ006 = !IN1 & !IN2 & IN3
# IN0 & IN1 & !IN2
# !IN0 & !IN1 & !IN2
# IN1 & !IN2 & !IN3
# !IN0 & !IN1 & IN3
# !IN0 & IN2 & IN3
# !IN0 & IN1 & !IN3
# IN0 & !IN1 & IN2;
-- Node name is 'E' from file "bcd7.tdf" line 25, column 17
-- Equation name is 'E', location is LC1_A24, type is buried.
E = LCELL( _EQ007);
_EQ007 = !_LC2_A24
# _LC3_A24
# !_LC4_A24
# !_LC5_A24;
-- Node name is 'E~1' from file "bcd7.tdf" line 25, column 17
-- Equation name is 'E~1', location is LC3_A24, type is buried.
-- synthesized logic cell
_LC3_A24 = LCELL( _EQ008);
_EQ008 = IN0 & IN1 & !IN2 & IN3
# !IN0 & !IN2 & !IN3
# !IN0 & IN2 & IN3
# !IN0 & IN1 & !IN3
# !IN1 & IN2 & IN3;
-- Node name is 'F' from file "bcd7.tdf" line 25, column 19
-- Equation name is 'F', location is LC8_B3, type is buried.
F = LCELL( _EQ009);
_EQ009 = !IN0 & IN3
# IN1 & IN3
# !IN2 & IN3
# !IN0 & !IN1
# !IN1 & IN2 & !IN3
# !IN0 & IN2;
-- Node name is 'G' from file "bcd7.tdf" line 25, column 21
-- Equation name is 'G', location is LC8_A24, type is buried.
G = LCELL( _EQ010);
_EQ010 = IN1 & IN3
# !IN2 & IN3
# !IN1 & IN2 & !IN3
# !IN0 & IN1
# IN1 & !IN2
# IN0 & IN3;
-- Node name is 'G~1' from file "bcd7.tdf" line 25, column 21
-- Equation name is 'G~1', location is LC6_B3, type is buried.
-- synthesized logic cell
_LC6_B3 = LCELL( _EQ011);
_EQ011 = IN0 & IN1 & !IN2 & !IN3
# IN0 & !IN1 & IN2 & IN3;
-- Node name is 'OUT0' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT0', type is output
OUT0 = G;
-- Node name is 'OUT1' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT1', type is output
OUT1 = F;
-- Node name is 'OUT2' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT2', type is output
OUT2 = E;
-- Node name is 'OUT3' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT3', type is output
OUT3 = D;
-- Node name is 'OUT4' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT4', type is output
OUT4 = C;
-- Node name is 'OUT5' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT5', type is output
OUT5 = B;
-- Node name is 'OUT6' from file "bcd7.tdf" line 27, column 6
-- Equation name is 'OUT6', type is output
OUT6 = A;
-- Node name is ':47' from file "bcd7.tdf" line 10, column 5
-- Equation name is '_LC3_B3', type is buried
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = LCELL( _EQ012);
_EQ012 = !IN0 & !IN1 & !IN2 & !IN3;
-- Node name is ':149' from file "bcd7.tdf" line 18, column 5
-- Equation name is '_LC5_A24', type is buried
!_LC5_A24 = _LC5_A24~NOT;
_LC5_A24~NOT = LCELL( _EQ013);
_EQ013 = !IN0 & !IN1 & !IN2 & IN3;
-- Node name is ':185' from file "bcd7.tdf" line 20, column 5
-- Equation name is '_LC4_A24', type is buried
!_LC4_A24 = _LC4_A24~NOT;
_LC4_A24~NOT = LCELL( _EQ014);
_EQ014 = !IN0 & IN1 & !IN2 & IN3;
-- Node name is ':265' from file "bcd7.tdf" line 25, column 5
-- Equation name is '_LC2_A24', type is buried
!_LC2_A24 = _LC2_A24~NOT;
_LC2_A24~NOT = LCELL( _EQ015);
_EQ015 = IN0 & IN1 & IN2 & IN3;
Project Information d:\zhuhui\mycpu\xianshi\bcd7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,063K
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